<mcc111[m]>
…also now that I'm looking at it… an LED on the… back of the device… is not really all that useful
<mcc111[m]>
i usually look at the front of a device, while i am using it
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<sporniket>
Hello, I am starting to use Component and Signature.
<sporniket>
Writing my first component, is there a mean to use the signature to generate the content of the ports() method ?
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<whitequark[cis]>
ports() method?
<whitequark[cis]>
are you talking about verilog.convert?
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<sporniket>
hum, since the beginning when I learned about amaranth, there was that method called "ports()" to add in the elaboratable to return a list of Signal. I know it is needed to see those signal in vcd files
<sporniket>
(e.g. in counterexample generated by formal verification)
<sporniket>
so I kind of thought of that port method as a must have.
<galibert[m]>
IIRC you get all signals in vcd files
<galibert[m]>
By default
<whitequark[cis]>
method? I'm very confused what are you talking about
<whitequark[cis]>
this is not a part of Amaranth and never has been
<whitequark[cis]>
it's just a thing some people chose to put in their elaboratables
<whitequark[cis]>
but yes, signatures can be introspected (there's a branch with the manual that shows how to do this... I'll post a link in a sec) so you can replace that of course
<whitequark[cis]>
rtlil.convert now knows about the signature
<whitequark[cis]>
(but you have to give it the elaboratable before it becomes a fragment)
<galibert[m]>
If dut has a signature just put a bare “dut” in there
<sporniket>
I see... thanks
<sporniket>
will work on that.
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<zyp[m]>
I'm looking into simulator mechanics and I wonder if there's a convenient way to model e.g. a DDR primitive that's responding to both edges of a clock signal that's passed in. I see Tick is based on self.add_trigger(domain.clk, trigger=1 if domain.clk_edge == "pos" else 0), so AIUI it's possible to wait for arbitrary edges, but it doesn't look like that's exposed to the testbench coroutines
<zyp[m]>
I'm not sure I have the full picture yet, but it seems to me like it'd be useful to have a sibling of Tick that instead of taking a domain, takes an arbitrary signal and optionally trigger level that gets passed directly to add_trigger()
<galibert[m]>
Aren't you going to have two domains or a double-speed single domain in the amaranth side anyway?
<zyp[m]>
I could for simulation, that's how I've worked around it in migen's simulator before, but the actual primitives act on both edges of a single clock
<zyp[m]>
if I haven't missed another obvious way to do this, this seems like a useful addition to me, that I can write a RFC for
<whitequark[cis]>
the reason this isn't currently implemented is that it's unclear that the yield Tick() style interface is particularly great and deserves expansion unmodified. the capability is obviously there.
<zyp[m]>
I see
<zyp[m]>
what sort of modification do you have in mind?
<whitequark[cis]>
I'm not actually sure (hence why it's not made or proposed yet) but it could be useful to watch on complex expressions rather than individual signals, and avoid new names in favor of using combinators of some kind
<whitequark[cis]>
I don't know, `await s.posedge()`? I'm quite unsure
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