00:44 <_whitenotifier-f> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/yosys/compare/3c3f21badc4b...0338c1cd0ed5

00:44 <_whitenotifier-f> [YoWASP/yosys] whitequark 0338c1c - Update dependencies.

21:17 <mcc111[m]> What is the amaranth equivalent of like always @(negedge audgen_sclk) begin ? in my other stuff i've been tracking "this was true on the last frame, now it's false" with a separate signal, is there something automated?

21:19 <zyp[m]> you can have a negative edge domain

21:20 <cr1901> m.d.domains.neg_clk = ClockDomain(clk_edge = "neg")

21:21 <cr1901> m.d.comb += ClockSignal("neg_clk").eq(ClockSignal("sync"))

21:21 <cr1901> ^did not test this, something like this

21:27 <adamgreig[m]> mcc111: do you just want to react to the falling edge of some io signal, or do you have a bunch of logic that specifically needs to run on the falling edge of a clock?

21:30 <mcc111[m]> adamgreig[m]: I'm porting some verilog code, in the original there's a audgen_sclk which creates a half-speed clock by banging a register up and down, and the verilog code I'm porting acts on the falling edge. I don't know why they picked the falling rather than rising edge

21:31 <adamgreig[m]> it might be better to just run your logic on every other one of your normal clock cycles, you can use EnableInserter for example around a whole submodule

21:32 <adamgreig[m]> sometimes there are specific reasons for doing otherwise but often it's best to just have the one clock and not try to make new clock signals out of logic and then clock other logic off of them

21:43 <mcc111[m]> <adamgreig[m]> "it might be better to just run..." <- How would you run logic on every other cycle without creating a clock out of logic?

21:45 <adamgreig[m]> when you wrap a submodule in EnableInserter, or equivalently just like with m.If(enable): bla, the logic inside is "gated", it only responds to changes when enable is high, which you toggle every clock (m.d.sync += enable.eq(~enable))

21:45 <adamgreig[m]> the enable is a clock in some sense, but it's not the clock that actually runs the digital logic

21:46 <adamgreig[m]> so all your flip-flops are still clocked by your main sync clock, just their "clock enable" input is connected to something that's only high half the time

21:46 <mcc111[m]> ok. it seems like that only works for exactly halving the clock tho

21:47 <adamgreig[m]> any rational division is more or less easy, like 1 in 4, or 3 in 4, whatever you drive that signal to

21:48 <adamgreig[m]> the motivation is that your logic remains all part of the same clock domain, so you don't need clock-domain-crossing logic to move signals around, and you aren't making a potentially glitchy clock out of logic and feeding it back into a global clock net, you can just keep your flops connected to the same global clock net as the ones they're talking to

22:14 <mithro> @whitequark[cis] Would it make sense for an amaranth module to be elaborated to RTLIL and then saved using `write_rtlil` to be later loaded and patched into a design (as opposed to writing out to verilog and then reading it in again)?