<cr1901>
(It's only a signed divider. I'll have to write an unsigned divider later when I'm up for it)
<whitequark[cis]>
nice!!!
<cr1901>
Tyvm :). Bedtime for me I think. Maybe I'll think of a way to combine an unsigned/signed divider while I sleep. One size-friendly way is to extend the divider inputs/outputs by one bit more than needed (to represent the entire unsigned range). Certainly better than two dividers :P.
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<galibert[m]>
I thought one could directly give objects with interfaces to ports=[...], I guess it's not in yet?
<whitequark[cis]>
you omit ports entirely
<galibert[m]>
ohhh
<galibert[m]>
TypeError: The convert() function requires a ports= argument
<whitequark[cis]>
I think it might be in a branch
<whitequark[cis]>
one sec
<galibert[m]>
Oh, I did a Fragment.get I shoudln't have done
<whitequark[cis]>
ahhh yeah
<whitequark[cis]>
that's a bit awkward yea
<galibert[m]>
It's better not to have to do the Fragment.get actually, so I like how it's now
<galibert[m]>
errr what, wishbone.Arbiter doesn't have a signature?
<whitequark[cis]>
we're still in process of migrating stuff
<whitequark[cis]>
I think jfng is working on this at the moment, but better ask him about it
<galibert[m]>
I guess, but jfng told me... yesterday? it was in
<galibert[m]>
" btw, feel free to try the new bus interfaces in amaranth-soc, they're in main now"
<galibert[m]>
now... am I up to date though?
<galibert[m]>
Yes, yes I am " wishbone.bus: migrate to lib.wiring interfaces."
<galibert[m]>
I guess there's an issue for how the Arbiter manages its interface
<galibert[m]>
more stuff to understand, cool :-)
<galibert[m]>
Hmmm, Arbiter._bus is an interface, but Arbiter itself doesn't have a signature
<galibert[m]>
I wonder if it's how it should be? I mean, you don't usually want to generate verilog for an arbiter itself, so it may not matter
<galibert[m]>
Or Arbiter should have a .signature with ._bus in it?
<galibert[m]>
Ok, I managed to make the Arbiter have a correct signature, need to PR that
<galibert[m]>
How short the commit is is, I think, a demonstration of how nice the design is in the first place
<galibert[m]>
So, I generate the verilog now, but there is a kink. The test adds two wishbone interfaces as targets, but the verilog generator does not pick them up as ports. Not sure it can. That's in large part why I thought giving a list of interfaces was useful
<jfng[m]>
galibert: the reason i've punted adding `.signature`s to Arbiter/Decoder primitives is that in the case of Decoders, the bus interface has a MemoryMap, which is assigned to it after creation:
<sporniket>
Do I understand correctly that all it takes is to declare something like m.d.comb += ClockSignal("my_new_domain").eq(myPll.clkout0) to bring the new clock domain "my_new_domain" into existence, or is there a catch ?