<jfng[m]>
<galibert[m]> "In wishbone, is there always one..." <- there at least one cycle with cyc & stb low between non-burst access, but otherwise not necessarily
<jfng[m]>
if LOCK is not supported by an arbiter, i think an initiator can own the bus indefinitely
<galibert[m]>
ok, so when switching initiators it's normal to have one cyc=0 cycle in between?
<galibert[m]>
and by normal I mean pretty much required?
<jfng[m]>
yes, if LOCK is unimplemented
<galibert[m]>
and if it is?
<whitequark[cis]>
the wishbone spec is really not very well defined, especially around interactions of features
<jfng[m]>
then the arbiter may switch initiators after an ACK is sent to the current owner
<jfng[m]>
and the lock signal is high, or sometjing like that
<galibert[m]>
so an arbiter should follow stb/ack to know where things are?
<galibert[m]>
And yeah Catherine , I agree with you, the spec is very light on that kind of subtleties
<jfng[m]>
not ack, but stb and lock if lock is supported