whitequark[cis] changed the topic of #amaranth-lang to: Amaranth hardware definition language · weekly meetings: Amaranth each Mon 1700 UTC, Amaranth SoC each Fri 1700 UTC · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang · Matrix #amaranth-lang:matrix.org
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<_whitenotifier-1> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/nextpnr/compare/3190f1c002e6...ec94d49655da
<_whitenotifier-1> [YoWASP/nextpnr] whitequark ec94d49 - Update dependencies.
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<mcc111[m]> I'm very excited about the amaranth tutorial device thing
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<SaketSinha[m]> .
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<galibert[m]> Of course it's more complicated than I expected, surprise, surprise
<galibert[m]> Is it possible to build a priority encoder on wishbone with zero latency?
<galibert[m]> (and by zero I mean less than one cycle)
<galibert[m]> the difficulty I have is how to avoid switching source when a higher priority initiator actives while a lower-priority bus access is in process while the latency requires the priority decision to be all comb
<galibert[m]> s/actives/activates/
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<galibert[m]> Hmmm, I think I have an idea
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<galibert[m]> Ok, I got something wrong, and I have pysim inflooping. How can I debug what I broke. Probably a comb loop, but I can't see it
<whitequark[cis]> there's no super good way to debug it
<whitequark[cis]> try outputting verilog and using verilator
<whitequark[cis]> the new IR will fix that
<galibert[m]> ok
<galibert[m]> I'm commenting/uncommenting regions and I'm getting something really weird...
<whitequark[cis]> yeah?
<galibert[m]> oh wow, I found what I could remove to kill the infloop (and the code) and it doesn't make much sense
<whitequark[cis]> yeah?
<galibert[m]> (very wip)
<galibert[m]> the unittest tests.test_wishbone_bus.ArbiterSimulationTestCase.test_simple (that's in amaranth-soc/wishbone) freezes
<galibert[m]> if I comment the else at lines 587-588 it doesn't
<galibert[m]> and it very much is not adding a loop
<galibert[m]> if I comment the two Elif-generating loops before it it still freezes
<whitequark[cis]> um, I cannot see any line numbers and Im on my phone
<whitequark[cis]> which lines?
<galibert[m]> while it's m.If(bus_busy): expression wth m.Else(): same expression
<galibert[m]> the else at the end
<whitequark[cis]> what is bus_busy and requests?
<galibert[m]> # Build the requests array
<galibert[m]> m.d.comb += requests.eq(Cat(intr_bus.cyc for intr_bus in self._intrs))
<galibert[m]> requests = Signal(len(self._intrs))
<galibert[m]> These two are already in the existing -soc arbiter
<galibert[m]> hmmm, I use bus_busy in a bunch of places, I should turn it into a signal and not that
<galibert[m]> Doesn't change a thing, sadly
<galibert[m]> lemme try to generate verilog to see
<galibert[m]> Argh, nmi-ed, later
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<_whitenotifier-f> [amaranth] implr commented on issue #725: Can I add typehints? - https://github.com/amaranth-lang/amaranth/issues/725#issuecomment-1722319379
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<_whitenotifier-f> [amaranth] whitequark commented on issue #725: Can I add typehints? - https://github.com/amaranth-lang/amaranth/issues/725#issuecomment-1722327777
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