whitequark[cis] changed the topic of #amaranth-lang to: Amaranth hardware definition language · weekly meetings: Amaranth each Mon 1700 UTC, Amaranth SoC each Fri 1700 UTC · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang · Matrix #amaranth-lang:matrix.org
<_whitenotifier> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/yosys/compare/daede40bbf86...67b4ef43da93
<_whitenotifier> [YoWASP/yosys] whitequark 67b4ef4 - Update dependencies.
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<cr1901> whitequark[cis]: For the following Amaranth code passed into verilog.convert with ports=None 1/2
<cr1901> I get the following output where two ports do not appear at the module definition: http://gopher.wdj-consulting.com:70/paste/c58f33ec-3024-4b52-85ad-5e5c33df2bae.txt
<cr1901> These wires in module sequencer DO EXIST!! They're just not marked as input/output: wr__data, and ctl__cmd__ops
<cr1901> What's interesting about these two particular wires in my working code is that I had to use as_value() to convert them to Signals() before the ports= input arg to verilog.convert was happy (m.ctl.cmd.ops and m.wr.data are both unions)
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<cr1901> Memo to self... sim.add_clock() takes a period. Not a frequency. So I was generating traces with periods of 12e6, and wondering why gtkwave was having a stroke loading them
<cr1901> I got nerdsniped and I wrote a working pipelined 8x8 multiplier. Uses amaranth.lib.data, but not wiring (b/c I couldn't figure out how to parameterize the signature): http://gopher.wdj-consulting.com:70/paste/79a90b88-5961-41c0-9dba-03b8b9532bbb.txt
<cr1901> Now that I got that out of my system... bedtime
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<whitequark[cis]> cr1901: I don't actually understand what the issue is here
<whitequark[cis]> does it work with #886?
<galibert[m]> Yeah, interfacing that code looks simple
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<cr1901> whitequark[cis]: No, it doesn't work with #886; Diamond dies with "Port ctl__cmd__ops does not exist"
<cr1901> which is correct; ctl__cmd__ops does not exist as a port, only as a wire.
<cr1901> But ctl__cmd__ops is part of the signature
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<cr1901> Wrapper().ctl.cmd.ops* is part of Wrapper's signature
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<whitequark[cis]> that's... interesting
<whitequark[cis]> please file an MCVE
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<_whitenotifier> [amaranth] cr1901 commented on pull request #886: back.{verilog,rtlil}: in convert(), accept a Component without ports - https://github.com/amaranth-lang/amaranth/pull/886#issuecomment-1703915790
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<cr1901> whitequark[cis]: Done
<whitequark[cis]> thanks!
<_whitenotifier> [amaranth-boards] whitequark commented on pull request #208: Initial support for Tang nano 9k board - https://github.com/amaranth-lang/amaranth-boards/pull/208#issuecomment-1703922332
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<_whitenotifier> [amaranth] whitequark opened pull request #895: vendor.GowinPlatform: oscillator improvements - https://github.com/amaranth-lang/amaranth/pull/895
<_whitenotifier> [amaranth] codecov[bot] commented on pull request #895: vendor.GowinPlatform: oscillator improvements - https://github.com/amaranth-lang/amaranth/pull/895#issuecomment-1703945977
<cr1901> Huh, looks like I missed a whole bunch of messages due to scrollback being screwy.
<cr1901> > Uses amaranth.lib.data, but not wiring (b/c I couldn't figure out how to parameterize the signature) <-- well, uniterm has an example of parametric signatures (w/o using Component).
<cr1901> >hey, while I'm at it, are you using MachXO2 nextpnr? does it work? <-- Yes, it works last I checked a few months ago. But seeing as you already packaged it, that info prob doesn't matter :P.
<whitequark[cis]> yep, to make a parametric signature, I would suggest implementing a @property signature
<whitequark[cis]> and then returning an object with values you compute
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<cr1901> Everything but the top-level, and EFB Verilog instantiation has been ported. Incredibly, I transcribed the Verilog of this last module to Amaranth correctly the first time.
<cr1901> I will take this Murphy's Law violation and run