whitequark[cis] changed the topic of #amaranth-lang to: Amaranth hardware definition language · weekly meetings: Amaranth each Mon 1700 UTC, Amaranth SoC each Fri 1700 UTC · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang · Matrix #amaranth-lang:matrix.org
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<_whitenotifier-1> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/yosys/compare/73d3df2d3faa...61326be31e60
<_whitenotifier-1> [YoWASP/yosys] whitequark 61326be - Update dependencies.
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<mcc111[m]> <galibert[m]> "I have all of it (in amaranth-..." <- Wait. Do you mean "C++ which I could translate to python via an essentially mechanical human-mediated process" or is there some way to actually build C++ into amaranth
<mcc111[m]> (Assuming the former)
<cr1901> amaranth gets translated into C++. You can then use C++ to simulate Amaranth/make testbenches
<mcc111[m]> that's extremely interesting
<bob_twinkles[m]> Amaranth -> C++ is a general Yosys feature, cxxrtl
<charlottia> mcc111: here's an example in a relatively small project: https://github.com/charlottia/i2c_obs/blob/f3ed7b187367d244249f5bcbefea11dce23500b6/i2c_obs/cxxsim.py
<charlottia> You can also add blackboxes to swap out parts of the circuit for custom classes, which makes things real fun.
<mcc111[m]> Like… for mocking?
<bob_twinkles[m]> or simulating interactions with external hardware yeah
<charlottia> Yep!
<bob_twinkles[m]> or i guess internal hardware, like a hard DSP block
<charlottia> Or if there's a particularly slow circuit — you can substitute it out for a hand-written (non-programmable-logic-based) component to test other parts faster.
<mcc111[m]> i guess if this means i make a game in Amaranth I can ship a pc emulator on steam relatively easily lol
<mcc111[m]> * this means if i make
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<mcc111[m]> I successfully compiled, then altered, then re-installed via JTAG a systemverilog program to the Pocket! https://mastodon.social/@mcc/111021749800302023 it originally said "FPGA"
<mcc111[m]> systemverilog is actually kinda irritating and the python helper toolchain for systemverilog turns out to assume MacOS (or rather, it assumes you're running Quartus inside Docker, which I'm not) so I think my next step is to actually start trying to use Amaranth on the thing! maybe not until this weekend tho.
<whitequark[cis]1> nice!!!
<whitequark[cis]1> congratulations
<mcc111[m]> thanks!! :D i'm very excited how easy this was. usually this is the point int he project i get permanently stuck
<whitequark[cis]1> yeah!
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<galibert[m]> mcc111: I means C++ that only use adders and equality comparisons or range checks that can become equality comparisons
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<jer_emy[m]> charlotte: thank you for sharing that example, it’s a great reference!
<charlottia> <jer_emy[m]> "charlotte: thank you for sharing..." <- Glad to hear it! You may also find some things of interest in the `vsh` stuff here. CXXRTL black boxes are used in 3 different ways — https://github.com/charlottia/sh1107
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<zyp[m]> do you have any performance numbers for it? I'm curious how much faster cxxsim is compared to pysim
<galibert[m]> Multiple orders of magnitude
<galibert[m]> No precise numbers handy but at least 1000x, possibly more
<zyp[m]> yeah, I was expecting «how much faster» to be «how many orders of magnitude»
<galibert[m]> there's a point after which comparing starts not to be significant anymore
<zyp[m]> true
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<_whitenotifier-1> [amaranth-soc] jfng commented on pull request #49: Migrate bus primitives to `amaranth.lib.wiring` - https://github.com/amaranth-lang/amaranth-soc/pull/49#issuecomment-1710094901
<_whitenotifier-1> [amaranth-soc] whitequark commented on pull request #49: Migrate bus primitives to `amaranth.lib.wiring` - https://github.com/amaranth-lang/amaranth-soc/pull/49#issuecomment-1710121958
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<sporniket> hello, since last time I got rid of the 'Past(...)' (pun obviously intended) ;
<sporniket> now I am attempting to write a TMDS encoder with the goal of getting something on screen from my colorlight board, and thus have 2 questions :
<sporniket> 1st question : how to link an Elaboratable to a given clock ?
<sporniket> I would naïvely specify the clock domain trough a constructor (def __init__(self,...,*,cd:ClockDomain):...)
<galibert[m]> Will that elaboratable have more than one clock?
<sporniket> and then in the elaborate : m = Module() ; m.domains.sync = self.cd (stored in the constructor)
<sporniket> no
<sporniket> it would have a single clock
<sporniket> being the pixel clock
<galibert[m]> then you use sync transparently in the Elaboratable, and you DomainRenamer when calling the constructor
<galibert[m]> m.submodules.hvideo = hvideo = DomainRenamer(self.video.name)(HDMIVideo())
<galibert[m]> where self.video is the pixel clock domain
<sporniket> I see
<sporniket> 2nd question : is there somewhere a known test suite for TMDS encoder to verify the output, i.e. : "when input data is xxx and the balance counter is n, then output data is yyy and the new balance counter is m" for a set of xxx/counter ?
<sporniket> I can write my own test suite of course https://github.com/sporniket/amaranth-stuff/issues/19
<sporniket> but if someone has already established a set of interesting values for validating the encoding...
<sporniket> I would gladly use it
<galibert[m]> Well, I have an adv encoder handy, so I didn't have to do that :-)
<sporniket> no problem
<sporniket> thanks
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<mcc111[m]> Embarrassingly basic question but I've been away from Python awhile.... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/jyZuNsKrPxuZVqQUYJmqlBDm>)
<mcc111[m]> can't import .. basically lol
<galibert[m]> you can actually
<galibert[m]> from ..core.core import YourClass I think works
<mcc111[m]> wow
<galibert[m]> don't think you can go higher than ..
<cr1901> you can. And I think Amaranth does
<whitequark[cis]1> yep
<mcc111[m]> Looks like I can set a PYTHONPATH using _.env_file in pyproject.toml. although that might cause interference if a PYTHONPATH always needs to be set externally… hm.
<galibert[m]> you can append to sys.path
<mcc111[m]> galibert[m]: in pyproject?
<mcc111[m]> i find a packages = [ { include = "src" }, ] described on stackoverflow but i haven't found this in the pdm docs yet
<galibert[m]> no, in the .py itself (I think)
<mcc111[m]> yeah, what i was hoping to do was fix it in one place and have it apply in several
<cr1901> whitequark[cis]1: I haven't had a chance to test your new changes to #904 (that's today!), but they look good.
<galibert[m]> Yeah, I get you
<bob_twinkles[m]> you can modify sys.path but it's likely not the right solution 😅
<galibert[m]> there are no wrong solutions, only approximations of the correct one ;-)
<whitequark[cis]1> mcc111[m]: this won't change PYTHONPATH
<whitequark[cis]1> it only changes the built artifacts
<mcc111[m]> ok.
<mcc111[m]> i got addicted to crate:: in rust
<mcc111[m]> So
<mcc111[m]> OpenFPGA / the Analogue Pocket has many peripherals ( https://www.analogue.co/developer/docs/overview ) and a *slightly* idiosyncratic installation process
<mcc111[m]> So I think (?) it makes sense to give it its own board file
<mcc111[m]> What in amaranth-boards is a good thing to fork from if I'm targeting cyclone
<mcc111[m]> * OpenFPGA / the Analogue Pocket has many peripherals ( https://www.analogue.co/developer/docs/overview ) and a _slightly_ idiosyncratic installation process
<mcc111[m]> So I think (?) it makes sense to give it its own board file
<mcc111[m]> What in amaranth-boards is a good thing to fork from if I'm targeting cyclone v?
<mcc111[m]> de10 is cyclone-v i guess…
<mcc111[m]> Looks like most of the communication I want to do is over what Analogue calls "busses" https://www.analogue.co/developer/docs/bus-communication They probably just mean, like… regular wires… right
<whitequark[cis]1> groups of wires, really
<mcc111[m]> point
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<cr1901> whitequark[cis]1: https://libera.irclog.whitequark.org/amaranth-lang/2023-08-31#1693456045-1693456176; I'm trying to convert my use of ArrayLayout to word_select and am running into a snag 1/2
<cr1901> If I do "self.efb.dat_w.eq(
<cr1901> self.ctl.cmd.ops.word_select(8, 2 - curr_op))", I get View of (slice (sig ctl__cmd) 8:32) does not have a field 'word_select'
<cr1901> How do I convert ops back to an object w/ word_select() method?
<Wanda[cis]> .as_value()
<cr1901> Right, and I knew that T_T. Woooow... I'm having A DAY today
<cr1901> tyvm
<cr1901> TypeError: Part width must be a non-negative integer, not (- (const 2'd2) (sig curr_op)) <-- Yes, I agree in the general case, but I know apriori that curr_op can't be > 2
<cr1901> Using as_unsigned() as a fallback
<cr1901> Actually, as_unsigned() didn't work
<cr1901> Part width must be a non-negative integer, not (u (- (const 2'd2) (sig curr_op))) the hell?
<crzwdjk> Width has to be constant I think?
<crzwdjk> The offset can be variable but not the width
<Wanda[cis]> yup
<cr1901> I had the parameters backwards as well
<cr1901> parameters to word_select
<cr1901> Excellent, tyvm for the help... all fixed now
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