whitequark[cis] changed the topic of #amaranth-lang to: Amaranth hardware definition language · weekly meetings: Amaranth each Mon 1700 UTC, Amaranth SoC each Fri 1700 UTC · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang · Matrix #amaranth-lang:matrix.org
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<chuckmcm[m]> Fair enough, the question I started with was this, "How difficult would it be to make a default PLL clock work with all boards?" Specifically Lattice ICE40 boards for now, but later with the ECP5 boards as well. It seemed "reasonable" to me that one should be able to instantiate the board with `pllclock=100e6` or what ever your desired PLL clock frequency was, and then either make it the default `sync()` domain or its own
<chuckmcm[m]> `pllclock()` domain. I figured out how to adjust the `__init__` signature for platforms to include `**kwargs` at the end, and look for the `pllclock=<value>` in the argument list. Then started wrapping my head around `create_missing_domain` (rather than create the module(s) in `__init__`. There is a relatively low impact change which is to record the desired PLL clock frequency in a instance variable and then check for that
<chuckmcm[m]> variable during domain creation, but that "feels" a bit hacky to me, and so I have been wrapping my head around the `ResourceManager` class and basically the whole mindset of what amaranth is doing in order to be true to the design goals vs my idea of what is the right way to do something.
<whitequark[cis]> some boards do not have a PLL. some boards have pin conflicts if a PLL is instantiated, etc
<whitequark[cis]> I do not think that special-casing a single PLL is a good direction for the platform to evolve in
<whitequark[cis]> if you search the issue tracker, there is an issue for providing an unified interface to PLLs
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<galibert[m]> is there a recommended way to import lib.wiring?
<whitequark[cis]> from amaranth.lib import wiring; then if you'd like from amaranth.lib.wiring import In, Out
<galibert[m]> Arguably import wiring should give you In/Out, no ?
<whitequark[cis]> well wiring.In is a bit wordy
<galibert[m]> Sure is. I meant the same way import amaranth gives you the good stuff, import amaranth.lib.wiring / amaranth.lib.data could too, no?
<whitequark[cis]> it doesn't
<whitequark[cis]> from amaranth import * does
<galibert[m]> Oh, indeed, you're right
<whitequark[cis]> you can also use from amaranth.lib.wiring import *
<whitequark[cis]> it's set up for that
<whitequark[cis]> however people get allergic to long strings of import * and it is not entirely without cause
<whitequark[cis]> the recommendation is: (a) for the prelude, use from amaranth import * (preferred) or import amaranth as am (acceptable); (b) for other libraries, use from amaranth.lib import data, wiring, ... and prefix them with data.Struct etc
<whitequark[cis]> all of the names have been set up to make star imports and qualified uses possible
<galibert[m]> ok, lemme align with the recommendations then. In/Out sure qualify for a specific import
<whitequark[cis]> I actually chose wiring for wiring.In be long but not too long
<whitequark[cis]> e.g. component was a nonstarter because component.In is just absurd
<galibert[m]> I like that
<galibert[m]> I like short, rememberable names
<galibert[m]> Component is going to break if I forget to call super.init(), right?
<galibert[m]> s/.init/.\_\_init\_\_/
<whitequark[cis]> yes
<whitequark[cis]> well, define break?
<whitequark[cis]> you will still have working .signature
<galibert[m]> members creation
<whitequark[cis]> yeah
<whitequark[cis]> that won't work
<galibert[m]> so I shall not forget :-)
<galibert[m]> looks like I'm using yield Tick(), is that supposed to be bare yield now?
<whitequark[cis]> it's been bare yield since 0.1 (if you use add_sync_process)
<galibert[m]> Ah, I'm using add_process for some reason
<galibert[m]> Can I alternatively tickle two domains from a add_process or should I make an intermediate elaboratable to do that?
<galibert[m]> or I add two clocks maybe? Gonna experiement to see :-)
<whitequark[cis]> "tickle" as in yield Tick?
<galibert[m]> on that specific domain yes
<galibert[m]> dual-phase cpu module
<galibert[m]> (6502)
<galibert[m]> ok, so using a Component you lose the i_/o_ convention. Sane
<whitequark[cis]> sometimes you might still use it, e.g. if you would have two identically named ports otherwise
<galibert[m]> indeed
<whitequark[cis]> yep, that is a part of intended use
<galibert[m]> wasn't at all sure of the syntax, now I know
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<chuckmcm[m]> These are great concerns, I'll be sure to include them in my write up
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