whitequark[cis] changed the topic of #amaranth-lang to: Amaranth hardware definition language · weekly meetings: Amaranth each Mon 1700 UTC, Amaranth SoC each Fri 1700 UTC · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang · Matrix #amaranth-lang:matrix.org
<cr1901> Well I ported probably the most complex module of my design to Amaranth. Aside from messing up the direction of two signals in the Verilog interface, it worked the first (second) try.
<cr1901> So that's nice :)
<whitequark[cis]> nice! link?
<cr1901> Feedback (especially critique) welcome
<whitequark[cis]> why do you do IntEnumWithShape?
<whitequark[cis]> Amaranth's IntEnum is specifically designed to be a drop-in replacement in every way if you do not use shape=
<whitequark[cis]> (actually, after a change I'm planning, it will use literally the same base class, if I can make the metaclass trickery work)
<cr1901> 1 sec
<whitequark[cis]> https://github.com/cr1901/efbutils/blob/amseq/ufm_reader/ufm_reader/sequencer.py#L72-L114 I feel like I'm encouraging an antipattern with some design choices
<cr1901> Oh?
<whitequark[cis]> these things should probably be signature objects? like SequencerSignature = Signature({ ... })
<whitequark[cis]> there's no reason to inherit from Signature if you're not adding methods
<cr1901> Ahhh
<cr1901> And ot was originally Enum/EnumWithShape. I needed EnumWithShape b/c I needed a zero constant of 16-bits. But when I added my lone test for now, I needed to compare an enum to a signal.
<whitequark[cis]> there is a downside however
<cr1901> (So I did a bulk replace Enum => IntEnum)
* cr1901 is listening
<whitequark[cis]> if you inherit from Signature then your signature becomes incompatible to someone else's signature (unless they special case yours)
<whitequark[cis]> if you do FooSignature = Signature({ ... }) they are compared structurally
<whitequark[cis]> re EnumWithShape, can you explain what are you achieving by using from enum import IntEnum at all?
<whitequark[cis]> i.e. what is the reason you're not using from amaranth.lib.enum import IntEnum in all cases?
<whitequark[cis]> for code unrelated to Amaranth it works exactly the same as a normal enum
<whitequark[cis]> or at least intended to; if it doesn't it's a bug
<cr1901> Ooooh, I didn't realize the shape was optional
<whitequark[cis]> it is!
<whitequark[cis]> okay, the doc needs to be improved
<cr1901> Fixed locally
<cr1901> >they are compared structurally <-- yea, structural typing (correct term?) instead of nominal seems good to have here
<whitequark[cis]> yes, correct term
<_whitenotifier> [amaranth] whitequark opened pull request #884: docs: emphasize that `shape=` is optional - https://github.com/amaranth-lang/amaranth/pull/884
<_whitenotifier> [amaranth] whitequark commented on pull request #884: docs: emphasize that `shape=` is optional - https://github.com/amaranth-lang/amaranth/pull/884#issuecomment-1700144845
<cr1901> Yea, it's best to correct this now; I just realized that b/c of Python scoping, I have to change the order of signatures in my source file to avoid undefined names.
<cr1901> when converting to Foo = Signature({..})
<whitequark[cis]> aha, right
<_whitenotifier> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±2] https://github.com/YoWASP/nextpnr/compare/1ab5c213a40b...3e719c45335f
<_whitenotifier> [YoWASP/nextpnr] whitequark 3e719c4 - Update dependencies.
<_whitenotifier> [amaranth] codecov[bot] commented on pull request #884: docs: emphasize that `shape=` is optional - https://github.com/amaranth-lang/amaranth/pull/884#issuecomment-1700149722
<cr1901> Oh and Signature Objects aren't callable, (so I need to remove the inner parens in, say, Out(SeqWriteStreamSignature()),
* cr1901 is fixing now
<whitequark[cis]> what do you think about #884?
<_whitenotifier> [amaranth] cr1901 commented on pull request #884: docs: emphasize that `shape=` is optional - https://github.com/amaranth-lang/amaranth/pull/884#issuecomment-1700165646
<cr1901> whitequark[cis]: LGTM
<cr1901> I have pushed changed to amseq branch w/ your feedback, so make sure to refresh the page when you're ready
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<cr1901> https://github.com/cr1901/efbutils/blob/amseq/ufm_reader/ufm_reader/sequencer.py#L134 It occured to me I could've done e.g. ops[24:32], but it appears I didn't feel like multiplying by 8 last night :P
<cr1901> erm, ops[16:24]*
<_whitenotifier> [amaranth-lang/amaranth] github-merge-queue[bot] pushed 1 commit to gh-readonly-queue/main/pr-884-f95fe451861066ae7e3ae6c9eb85778de5e949e0 [+0/-0/±1] https://github.com/amaranth-lang/amaranth/commit/cfd4f9c84e6e
<_whitenotifier> [amaranth-lang/amaranth] whitequark cfd4f9c - docs/enum: emphasize that `shape=` is optional.
<_whitenotifier> [amaranth] github-merge-queue[bot] created branch gh-readonly-queue/main/pr-884-f95fe451861066ae7e3ae6c9eb85778de5e949e0 - https://github.com/amaranth-lang/amaranth
<_whitenotifier> [amaranth-lang/amaranth] github-merge-queue[bot] pushed 1 commit to main [+0/-0/±1] https://github.com/amaranth-lang/amaranth/compare/f95fe4518610...cfd4f9c84e6e
<_whitenotifier> [amaranth-lang/amaranth] whitequark cfd4f9c - docs/enum: emphasize that `shape=` is optional.
<_whitenotifier> [amaranth-lang/amaranth] github-merge-queue[bot] deleted branch gh-readonly-queue/main/pr-884-f95fe451861066ae7e3ae6c9eb85778de5e949e0
<_whitenotifier> [amaranth] whitequark closed pull request #884: docs: emphasize that `shape=` is optional - https://github.com/amaranth-lang/amaranth/pull/884
<_whitenotifier> [amaranth] github-merge-queue[bot] deleted branch gh-readonly-queue/main/pr-884-f95fe451861066ae7e3ae6c9eb85778de5e949e0 - https://github.com/amaranth-lang/amaranth
<whitequark[cis]> cr1901: one sec
<_whitenotifier> [amaranth-lang/amaranth-lang.github.io] whitequark pushed 1 commit to main [+0/-0/±36] https://github.com/amaranth-lang/amaranth-lang.github.io/compare/0e2f90e837be...997370dc2d6b
<_whitenotifier> [amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] 997370d - Deploying to main from @ amaranth-lang/amaranth@cfd4f9c84e6e7f89f4748434d21551f112704e73 🚀
<cr1901> whitequark[cis]: This might not be syntactically valid, but to create a just_entered... something like this at the bottom? http://gopher.wdj-consulting.com:70/paste/1cad8979-1f4c-4d3d-9b8f-7abbf75a616e.txt
<whitequark[cis]> you don't need the .width assignmetn
<whitequark[cis]> use prev_state = Signal.like(fsm.state)
<whitequark[cis]> otherwise yeah
<cr1901> Oh that's cool... when fsm.state's width changes prev_state will "know" about it
<whitequark[cis]> no
<whitequark[cis]> I'm suggesting you replace prev_state.width = fsm.state.width
<whitequark[cis]> by that point, fsm.state.width will never change again
<cr1901> Ooooh, alright, I see
<cr1901> Not going to place bets, but it might be possible I port a second module tonight
<whitequark[cis]> okay, this looks basically fine to me now
<whitequark[cis]> instead of invoking View directly like in https://github.com/cr1901/efbutils/blob/amseq/ufm_reader/ufm_reader/sequencer.py#L134
<whitequark[cis]> you could say ArrayLayout(...)(self.ctl.cmd.ops)
<whitequark[cis]> but your way is frankly more readable
<whitequark[cis]> also, that's a clever use of ArrayLayout!
<whitequark[cis]> though, now that I looked at it, uhm
<whitequark[cis]> you could use self.efb.dat_w.eq(op_view.word_select(8, curr_op)) instead of the entire Switch
<whitequark[cis]> actually that has wrong endianness, I guess it'd be self.efb.dat_w.eq(op_view.word_select(8, 2 - curr_op))
<whitequark[cis]> same difference
<cr1901> Ack, I'll fix that in the morning
<cr1901> Well actually tomorrow night, taking a day trip to beach tomorrow
<whitequark[cis]> o/
<cr1901> http://gopher.wdj-consulting.com:70/paste/87b0e8d5-8ab8-4e6f-a9e0-962d16e9efc3.txt In the meantime, here's the next module converted. Not tested, but Verilog is emitted.
<cr1901> Would appreciate comments when you get the chance and I'll get back to them tomorrow night
<whitequark[cis]> .cmd.cmd?
<cr1901> In retrospect it should be cmd.name, I didn't change the name yet.
<whitequark[cis]> I feel like next_state_if_asserted doesn't pull its weight. everyone knows what m.If(): m.next does
<cr1901> Fair, it was a Verilog task I copied verbatim
<whitequark[cis]> same for assert_if_just_entered
<whitequark[cis]> ah right
<whitequark[cis]> clever use of ** at the beginning
<whitequark[cis]> I think your Amaranth has improved a lot in the last few months
<cr1901> Appreciated :). I think it helps that this is a project I enjoy a lot.
<whitequark[cis]> ^^ I'm glad
<cr1901> And that a working Verilog code already existed (so I can focus on rewriting in Amaranth, and not so much "how does the logic work?")
<cr1901> Lattice doesn't make it exactly easy to use the MachXO2 internal IP. This started out a Diamond project just to get a feel for how to interface to the EFB, but my intent was always to port it to Amaranth (it lives in the amaranth dir on my machine :P).
<whitequark[cis]> I see!
<cr1901> When it's working completely in Amaranth, next plan is to parameterize PageBuffer; it should be useable as a small cache for designs which read from SPI Flashes or anything w/ a page-at-a-time interface.
<cr1901> So like how AT2XT is my pet project for Rust/something I enjoy, EFButils will be my pet project for Amaranth; it'll evolve as the language evolves :)
<whitequark[cis]> nice!
<whitequark[cis]> we will eventually want to have that in, probably, stdio
<galibert[m]> Do we have examples of dynamically generated interfaces handy? In my case I have the width coming in as a constructor parameter
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<crzwdjk> galibert[m]: I have some in my project, https://github.com/crzwdjk/uniterm
<galibert[m]> thanks
<galibert[m]> cursor is a good example, much thanks
<crzwdjk> np, let me know if you have questions (or suggestions)
<whitequark[cis]> crzwdjk: do you want feedback on your code?
<crzwdjk> Yeah, I wouldn't mind feedback
<whitequark[cis]> it's actually the same as to @cr1901 yesterday
<whitequark[cis]> consider this file for example: https://github.com/crzwdjk/uniterm/blob/main/gateware/signatures.py
<whitequark[cis]> you could inherit from Signature but there are downsides, namely it does not compare equal to any other instance of itself
<whitequark[cis]> so unless you need to inherit (to define methods) it's better to define a constant or a function
<whitequark[cis]> that also makes it clear to downstream code that nothing weird is happening in the class
<crzwdjk> Got it, I'll add that to my todo list of cleanups
<whitequark[cis]> looks fine to me otherwise!
<crzwdjk> It needs some tweaks because it barely passes timing now, but otherwise interfaces have really made things much easier
<crzwdjk> The first time around I tried to make this, there were several times I spent a couple hours wondering why it doesn't work until I found the typo where I wired things up the wrong way around or forgot to connect some signal
<crzwdjk> I also have an ANSI escape code parser I need to port over. Which btw has something like cr1901's next_state_if_asserted helper except it does a bit more, pulling an item of data from a stream.
<whitequark[cis]> <crzwdjk> "It needs some tweaks because..." <- I'm really glad to hear it did!
<whitequark[cis]> I'm also happy to see that people are largely (except for the one thing I highlighted) using interfaces as I intended
<_whitenotifier> [YoWASP/nextpnr] whitequark pushed 2 commits to develop-0.6 [+0/-0/±2] https://github.com/YoWASP/nextpnr/compare/fcea994be0da...32311712f362
<_whitenotifier> [YoWASP/nextpnr] whitequark 812dd1a - [autorelease] Use PyPI Trusted Publishing.
<_whitenotifier> [YoWASP/nextpnr] whitequark 3231171 - [autorelease] Update dependencies.
<whitequark[cis]> cr1901: hey, while I'm at it, are you using MachXO2 nextpnr? does it work?
<whitequark[cis]> I can package it in yowasp
<_whitenotifier> [YoWASP/nextpnr] whitequark pushed 2 commits to release-0.6 [+0/-0/±2] https://github.com/YoWASP/nextpnr/compare/fcea994be0da...32311712f362
<_whitenotifier> [YoWASP/nextpnr] whitequark 812dd1a - [autorelease] Use PyPI Trusted Publishing.
<_whitenotifier> [YoWASP/nextpnr] whitequark 3231171 - [autorelease] Update dependencies.
<_whitenotifier> [YoWASP/nextpnr] whitequark pushed 1 commit to machxo2 [+6/-0/±3] https://github.com/YoWASP/nextpnr/commit/8042bcda8494
<_whitenotifier> [YoWASP/nextpnr] whitequark 8042bcd - Add Lattice MachXO2 toolchain support.
<_whitenotifier> [nextpnr] whitequark created branch machxo2 - https://github.com/YoWASP/nextpnr
<_whitenotifier> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+6/-0/±4] https://github.com/YoWASP/nextpnr/compare/3e719c45335f...488b23dd35d1
<_whitenotifier> [YoWASP/nextpnr] whitequark 488b23d - Add Lattice MachXO2 toolchain support.
<_whitenotifier> [YoWASP/nextpnr] whitequark deleted branch machxo2
<_whitenotifier> [nextpnr] whitequark deleted branch machxo2 - https://github.com/YoWASP/nextpnr
<_whitenotifier> [amaranth] whitequark commented on issue #882: Unfriendly "recursion depth exceeded" error message when forgetting `In` and `Out` on a `Component`'s signature - https://github.com/amaranth-lang/amaranth/issues/882#issuecomment-1701583361
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<_whitenotifier> [amaranth] whitequark opened pull request #885: lib.wiring: fix equality of `FlippedSignature` with other object - https://github.com/amaranth-lang/amaranth/pull/885
<_whitenotifier> [amaranth] codecov[bot] commented on pull request #885: lib.wiring: fix equality of `FlippedSignature` with other object - https://github.com/amaranth-lang/amaranth/pull/885#issuecomment-1701601688
<_whitenotifier> [amaranth-lang/amaranth] github-merge-queue[bot] pushed 1 commit to gh-readonly-queue/main/pr-885-cfd4f9c84e6e7f89f4748434d21551f112704e73 [+0/-0/±2] https://github.com/amaranth-lang/amaranth/commit/6b59ecda1b34
<_whitenotifier> [amaranth-lang/amaranth] whitequark 6b59ecd - lib.wiring: fix equality of `FlippedSignature` with other object.
<_whitenotifier> [amaranth] github-merge-queue[bot] created branch gh-readonly-queue/main/pr-885-cfd4f9c84e6e7f89f4748434d21551f112704e73 - https://github.com/amaranth-lang/amaranth
<_whitenotifier> [amaranth-lang/amaranth] github-merge-queue[bot] deleted branch gh-readonly-queue/main/pr-885-cfd4f9c84e6e7f89f4748434d21551f112704e73
<_whitenotifier> [amaranth] github-merge-queue[bot] deleted branch gh-readonly-queue/main/pr-885-cfd4f9c84e6e7f89f4748434d21551f112704e73 - https://github.com/amaranth-lang/amaranth
<_whitenotifier> [amaranth-lang/amaranth] github-merge-queue[bot] pushed 2 commits to gh-readonly-queue/main/pr-885-cfd4f9c84e6e7f89f4748434d21551f112704e73 [+0/-0/±3] https://github.com/amaranth-lang/amaranth/compare/44d5fac01cf6^...88cbf3012898
<_whitenotifier> [amaranth-lang/amaranth] whitequark 44d5fac - lib.wiring: fix equality of `FlippedSignature` with other object.
<_whitenotifier> [amaranth-lang/amaranth] whitequark 88cbf30 - lib.wiring: use `is` for type comparison in `Component`.
<_whitenotifier> [amaranth] github-merge-queue[bot] created branch gh-readonly-queue/main/pr-885-cfd4f9c84e6e7f89f4748434d21551f112704e73 - https://github.com/amaranth-lang/amaranth
<_whitenotifier> [amaranth-lang/amaranth] github-merge-queue[bot] pushed 2 commits to main [+0/-0/±3] https://github.com/amaranth-lang/amaranth/compare/cfd4f9c84e6e...88cbf3012898
<_whitenotifier> [amaranth-lang/amaranth] whitequark 44d5fac - lib.wiring: fix equality of `FlippedSignature` with other object.
<_whitenotifier> [amaranth-lang/amaranth] whitequark 88cbf30 - lib.wiring: use `is` for type comparison in `Component`.
<_whitenotifier> [amaranth] whitequark closed pull request #885: lib.wiring: fix equality of `FlippedSignature` with other object - https://github.com/amaranth-lang/amaranth/pull/885
<_whitenotifier> [amaranth-lang/amaranth] github-merge-queue[bot] deleted branch gh-readonly-queue/main/pr-885-cfd4f9c84e6e7f89f4748434d21551f112704e73
<_whitenotifier> [amaranth] whitequark closed issue #882: Unfriendly "recursion depth exceeded" error message when forgetting `In` and `Out` on a `Component`'s signature - https://github.com/amaranth-lang/amaranth/issues/882
<_whitenotifier> [amaranth] github-merge-queue[bot] deleted branch gh-readonly-queue/main/pr-885-cfd4f9c84e6e7f89f4748434d21551f112704e73 - https://github.com/amaranth-lang/amaranth
<_whitenotifier> [amaranth-lang/amaranth-lang.github.io] whitequark pushed 1 commit to main [+0/-0/±32] https://github.com/amaranth-lang/amaranth-lang.github.io/compare/997370dc2d6b...47c7cf130c53
<_whitenotifier> [amaranth-lang/amaranth-lang.github.io] github-merge-queue[bot] 47c7cf1 - Deploying to main from @ amaranth-lang/amaranth@88cbf3012898e1c42041eefa0ea4bba0d81942e9 🚀
<whitequark[cis]> so it turns out the logic for flattening a Signature into a list of ports is actually quite not trivial]
<whitequark[cis]> especially once dimensions get involved
<_whitenotifier> [rfcs] whitequark opened pull request #25: Amend RFC #2 to add `Signature.flatten` - https://github.com/amaranth-lang/rfcs/pull/25
<_whitenotifier> [amaranth] whitequark opened pull request #886: back.{verilog,rtlil}: in convert(), accept a Component without ports - https://github.com/amaranth-lang/amaranth/pull/886
<whitequark[cis]> @cr1901 (and others): try https://github.com/amaranth-lang/amaranth/pull/886
<whitequark[cis]> cc galibert
<_whitenotifier> [amaranth] codecov[bot] commented on pull request #886: back.{verilog,rtlil}: in convert(), accept a Component without ports - https://github.com/amaranth-lang/amaranth/pull/886#issuecomment-1701749557
<_whitenotifier> [YoWASP/nextpnr] whitequark pushed 2 commits to release [+6/-0/±6] https://github.com/YoWASP/nextpnr/compare/1ab5c213a40b...488b23dd35d1
<_whitenotifier> [YoWASP/nextpnr] whitequark 3e719c4 - Update dependencies.
<_whitenotifier> [YoWASP/nextpnr] whitequark 488b23d - Add Lattice MachXO2 toolchain support.
<_whitenotifier> [amaranth] whitequark commented on issue #883: Infer Verilog ports on Interface objects - https://github.com/amaranth-lang/amaranth/issues/883#issuecomment-1701755879
<galibert[m]> Interesting
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<cr1901> whitequark[cis]: Just got back from beach trip, will try after I get ready for the night