azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<agg>
anyone know why an ecp5 ddr output (ODDRX1F) seems to be 2 cycles more latency to the pin than an sdr registered output (OFS1P3DX) fed from the same data and clock?
<agg>
I can't find anything in the lattice docs that says how much latency either has, and as far as I can see nothing else is creeping in to the design before it's given to nextpnr
<agg>
ah, nevermind, I see with more searching that this is indeed just A Thing