azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<tnt> Anybody see anything wrong with that verilog snippet https://pastebin.com/nWiXDS1d that would cause undefined behavior / mis-synthesis ? Works fine in yosys and synplify and iverilog but LSE output is wrong.
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<jevinskie[m]> No looks fine to me. Granted I’m a VHDL guy but even that is so simple it should work. Have you tried synthesizing just that as a module and looking at the fitter RTL?
<tnt> jevinskie[m]: yeah, I made a test case. LSE just screws it up. The post synth verilog doesn't behave in simulation like the rtl does.
<tnt> So pretty sure it's a LSE bug.
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<ZipCPU> tnt: Yeah, I see a problem: How is samp_sync set? You haven't given an initial value to samp_cnt, so if it doesn't get an initial value somehow, it'll never transition from 'xxx
<jevinskie[m]> Sounds like it. Maybe it is part of the secret backdoor (jk) but I’ve always wondered about the possibility in synthesis tools https://www.wired.com/2016/06/demonically-clever-backdoor-hides-inside-computer-chip/
<jevinskie[m]> Doh yes the combinatorial path!
<tnt> ZipCPU: In the minimal test case, I just take that signal as top level io to the fpga.
<ZipCPU> samp_sync is top level IO?
<ZipCPU> That's a clock domain crossing issue
<ZipCPU> It needs to be synchronized to the clock
<tnt> Here's the exact (and single file) I feed to LSE to reproduce the bug.
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<ZipCPU> You need a 2FF synchronizer, not a 1FF synchronizer.
<ZipCPU> Also, without reset or initial value, you should expect an initial glitch.
<tnt> ... this shows up in post-synth simulation ... no metastability in modelsim.
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