azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<tnt>
Has anyone used the 50ns filter/delay blocks in the up5k ? Are those separate primitives ?
<gatecat>
in icebox, and I think Radiant, they are, in icecube its an attribute
<gatecat>
but afaik they aren't implemented at all in nextpnr or arachne currently
<tnt>
I don't even see anything in the chipdb
<tnt>
Only some info on the ultraplus html page for SB_FILTER_50NS (and nothing about SB_DELAY_50NS ?)
<gatecat>
ah, maybe it only made it to the html
<gatecat>
I think delay and filter are the same thing?
<tnt>
I'm not sure ... I can't even really find any docs about them at all from lattice
<tnt>
There seem to be a distinct SB_FILTER_50NS and SB_DELAY_50NS in sbt_backend/devices/ice40UP5K.lib
<gatecat>
huh
<tnt>
and in the up5k user guide graphics they also show as different blocks ... but then that's the only places I see them.
<tnt>
And "Aug28,2015 Remove primitives SB_DELAY_50NS and SB_FILTER_50NS. Brian Tai."
<gatecat>
yeah, you're right
<gatecat>
SCL_INPUT_FILTERED and SDA_OUTPUT_DELAYED are both attributes according to the SB library
<gatecat>
(afaik the primitives disappeared because they became attributes on the I2C IP, but from a hardware point of view they are still seperate)
<tnt>
There is also an "i2c fifo" buried somewhere in there ?
<tnt>
no clue what that's about
<gatecat>
that's for a different iCE40
<gatecat>
I think the original Ultra?
<tnt>
Oh yeah, that's the hard ip for the UltraLite
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