20:33 <kittennbfive> Hello experts! Is there a way with Yosys to get a FIFO using the EBR of the ECP5? There is no primitive for this and i obviously don't have they proprietary software...

20:34 <kittennbfive> Or a more open question, do we have a tool like ecppll but for all these different RAM-types?

20:36 <gatecat> unless you have some very special requirement, I think finding some regular FIFO Verilog and letting BRAM be inferred should be fine

20:37 <tnt> kittennbfive: sync or async would be the first question.

20:38 <kittennbfive> tnt: I am sorry, i am a beginner. I have a common clock for both sides, it is that what you mean? I need a FIFO because some part of my design reacts to external events and some other part spits out data over an UART and that is somewhat slower, so i need some buffer.

20:39 <kittennbfive> gatecat: So Yosys will automatically use BRAM if needed?

20:39 <tnt> yes, same clock = sync fifo.

20:40 <tnt> kittennbfive: look at fifo_sync_ram.v in https://github.com/no2fpga/no2misc/tree/master/rtl . ( and it uses ram_sdp.v to "infer" ram blocks ).

20:43 <kittennbfive> thank you, i will try this

20:49 <kittennbfive> ok, so indeed Yosys infers some DP16KD when using ram_sdp.v. I will study this code to understand how it works exactly (as i said, beginner here). Thanks again.

21:20 <kittennbfive> just a quick note for the Yosys-people: The Link to the pdf-manual on https://yosyshq.net/yosys/documentation.html is broken.