azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<tnt>
Is there anyway in verilog or systemverilog to set module parameters from something I'd read from a file ?
<tnt>
I'm basically trying to emulate the "INIT_FILE" params the OSS toolchain has for SB_RAM40_4K in radiant using PDP4K primitives.
<mwk>
nope, that's pretty much impossible in sv's elaboration sequence
<mwk>
best you can do is hack something up with `include
<tnt>
That's unfortunate :/ But tx for the confirmation.