azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs:
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<gatecat> agg: yeah it's one of the really annoying things Lattice do
<gatecat> I think the latency comes from registers also used for CDC in the higher gearing (4:1) modes
<tnt> That's might biggest gripe with the ecp5/nx IOs ... DDR sucks
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<agg> Aw, it's the same on nx? It is indeed extremely annoying
<gatecat> yeah
<tnt> nx is very close to ecp5 AFAIK.
<gatecat> the only significant difference in terms of the high-speed IO stuff is new x8/x10 modes
<tnt> yeah, that's pretty nice. Also isn't there something about the 4:1 mode that's officially supported in NX and only supported in nextpnr for the ECP% ?
<tnt> OE control maybe IIRC ?
<tnt> (like bidir)
<gatecat> 4:1 input and output at the same time is the problem
<gatecat> I think it's the same for NX, not officially supported, although that stuff hasn't been implemented at all in nextpnr so I can't test if it works in hardware like ECP5 (I expect it will given how similar the logic is though)
<tnt> I think for the NX it's documented as supported whihc is why I was surprised it wasn't for the ECP5.
<gatecat> ah interesting
<tnt> It's like >1y ago so ... maybe my memory is playing tricks.
<gatecat> it is officially supported for ECP5 when using the DQS stuff, just not otherwise
<tnt> Oh there is Radiant 3.0 ... hadn't even seen that.
<tnt> This works in Radiant without issues, which I think doesn't for ECP5 in diamond.
<tnt> No 4:1 for OE though AFAIK.
<tnt> Oh ... it didn't even pack the OE register into the PIC either, there is a warning saying it got moved to SLICE.
<tnt> Those PIO block are weird.
<gatecat> oh, excellent, thanks for testing
<gatecat> tbh, given how similar the IO is, its more evidence that it was intended to work in hw on ECP5 too and it was just an oversight in Diamond not to support it
<tnt> yup
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