azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<jevinskie[m]>
Does migen or nmigen support a non-default clock domain for FSMs? Looking though the code I can’t find examples of that or the provisions for it
<tnt>
jevinskie[m]: with m.FSM(domain="blah"): I think ?
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<jevinskie[m]>
tnt: doh! Thanks I was looking at nmigen’s compat module which doesn’t have the domain parameter!
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<jevinskie[m]>
Whew I was able to hack up something for migen/litex. Added a _cd2sync attribute to Module that returns a proxy object. mod._cd2sync[“jtag”] += foo is equivalent to mod.sync.jtag += foo and you can give it a dynamic clock domain key :)
<jevinskie[m]>
Ah this is what ClockDomainsRenamer is for isn’t it?
<whitequark>
in nmigen you can use `m.d["jtag"] +=` for this purpose