azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Code: https://github.com/azonenberg/openfpga. Channel logs: https://libera.irclog.whitequark.org/##openfpga
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<Zorix> is that necessary?
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<sorear> Zorix: https://github.com/Libera-Chat/libera-chat.github.io/commit/cf52115 did you see the global notice
<Zorix> didn't see the global notice.. not sure what that has to do with that
<sorear> what are you talking about then
<Zorix> nick change spam
<sorear> if you don't use the nicknames you will lose them, per the rule change I just linked
<Zorix> seems reasonable
<jevinskie[m]> Has anyone experimented or taken a stab at hierarchical verilog generation from migen? It would really help the VCD viewing and FPGA utilization reports.
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<zyp> jevinskie[m], that's one of the improvements you'll get from nmigen
<zyp> if you want hierarchical verilog, it's probably more worthwhile to port stuff to nmigen rather than attempt to add it to migen
<whitequark> there's also a compatibility layer
<whitequark> `from nmigen.compat import *`
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azonenberg changed the topic of ##openfpga to: Open source tools for FPGAs, CPLDs, etc. Silicon RE, bitfile RE, synthesis, place-and-route, and JTAG are all on topic. Channel logs: https://libera.irclog.whitequark.org/~h~openfpga
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<jevinskie[m]> Excellent news about nmigen! I’m using litex now so I’ll probably have to port the litex stream bits to nmigen and then include the generated verilog. Thanks!
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<agg> New lattice certuspro-nx looks like a nice ecp5 replacement https://www.latticesemi.com/about/newsroom/pressreleases/2021/202130certuspronx
<agg> 50 or 100k LEs, bunch of memory and 18bit multipliers, same sort of packages as ecp5, 10G serdes standard
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