ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<ikskuh> oh god
<ikskuh> verilog simulation is having race conditions?
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<killjoy> Never underestimate the lowest common denominator.
<killjoy> (This is regards to krb asking about musical synthesizers.)
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<lofty> So, could somebody better at Verilog than me tell me if signedness matters for a reduce-AND (unary &)
<lofty> e.g. if there's a case where `&$signed(X) != &$unsigned(X)`
<lofty> Because I don't think there is but I'm not a language lawyer
<lofty> (this is relevant because Yosys has an input signedness parameter to $reduce_and)
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