ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<sagar_acharya> I need small help. I'm unable to determine what pin to set in pcf file for output reg video in above verilog file.
<sagar_acharya> For hsync and vsync, there is DPIO pin type with bank 3.
<sagar_acharya> What is PIO and DPIO?
<sagar_acharya> What is bank? For now, I merely translate using pinout sheet
<Sarayan> what's your hardware? That code seems to be generating a monochrome digital signal
<sagar_acharya> hx8k olimex board
<sagar_acharya> iCE40
<Sarayan> iCE40-IO board for vga?
<sagar_acharya> yes
<sagar_acharya> What pins to assign? What is DPIO and PIO?
<sagar_acharya> What is bank?
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<Sarayan> video should go to all nine VGA_{RED,GREEN,BLUE}[1-3]
<sagar_acharya> Ok, so I did test, the video code of olimex
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<sagar_acharya> As at above pcf
<sagar_acharya> Lines 223-225 assign combined_pixel to video which I think should be the video in case video isn't off.
<sagar_acharya> In video_generator.v
<sagar_acharya> Alright, understood
<sagar_acharya> I have to change quite some code in video_generator, Thanks Sarayan!
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