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<machinehum>
tnt: Why is usb3 so impossible? Not enough logic cells?
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<machinehum>
tnt: From googleing around I've found a bunch of your stuff. no3usb looks really interesting, what would be the limitations of getting it to work with HS?
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<ikskuh>
what's the verilog equivalent to a VHDL procedure?
<ikskuh>
i've searched a bit but tasks aren't meant to be used in synthesis?
<gatecat>
I'm pretty sure Yosys can synthesise tasks
<gatecat>
it can definitely synthesise functions
<ikskuh>
okay, cool. i'll try!
<ikskuh>
it's definitly easier to handle recurring tasks with it
<ikskuh>
is there something like enums?
<ikskuh>
or do i just create a huge amount of localparam ?
<gatecat>
enums should be supported in systemverilog mode (`read -sv`/`read_verilog -sv`, or automatic with a .sv extension and files passed on the command line)
<ikskuh>
i think iverilog doesn't like sv :(
<lambda>
are you sure you don't want to just use VHDL? :p
<ikskuh>
looks like verilog is more widespread
<ikskuh>
and i have more fun with verilog, but also like strict typing
<ikskuh>
it's also very satisfying to remove bits from your design as they are unnecessary
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<killjoy>
It looked to me that iverilog can use sv if you specify -g2012 to it.
<killjoy>
But I haven't tested this, it's just what the googles says.
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