ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<ikskuh> hmm
<ikskuh> i've got a sticky reg and i have no idea why it sticks
<ikskuh> how could i debug this?
<lambda> what's a sticky reg?
<ikskuh> i have a "reg vsync"
<ikskuh> which i assign 0 in reset, and have two conditions where one sets it to 1 and the other sets it to 0
<ikskuh> but the set to 0 never seems to happen
<lambda> in hardware or in simulation?
<ikskuh> hw
<ikskuh> simulation is next /o\
<ikskuh> i really should simulate before i prog
<lambda> yeah, try that, also make sure you're meeting timing
<ikskuh> i have pll to 160 mhz, synthesis tells me 296 mhz should be good
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<ikskuh> oh yeah, 25 MB vcd file \o/
<lambda> that's pretty compact!
<ikskuh> heh
<ikskuh> i'm trying to implement VGA (again)
<ikskuh> have done it successfully in VHDL already
<ikskuh> but learning the whole yosys+iverilog way right now
<lambda> that's always fun to implement :) and it's fairly easy to slap DVI/HDMI on top, too
<ikskuh> yeah
<ikskuh> i wanna built my own computer and stuff
<ikskuh> i've learnt that DVI is just serial VGA
<ikskuh> huh, weird
<ikskuh> it's also sticky in the sim
<lambda> hooray, much easier to debug! :)
<ikskuh> localparam vga_vs_end = vga_height + vga_hs_frontporch + vga_vs_syncpulse;
<ikskuh> reading code would've helped too /o\
<ikskuh> that was one heck of a stupid mistake
<lambda> oh, whoops
<ikskuh> let's see what happens when i now measure ^^
<ikskuh> screen is white \o/
<lambda> cool!
<ikskuh> now let's do colors!
<ikskuh> works
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