ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<ikskuh> and another rubber ducking is necessary
<ikskuh> i have a memory "reg [7:0] framebuffer [15:0];" with 32k bytes size
<ikskuh> and i have a wire accessing this based on the x address of the vga
<ikskuh> wire [7:0] current_color_index = framebuffer[img_x[7:0]];
<ikskuh> and i output that index to rgb in the pixel process
<ikskuh> but it seems like it's only respecting the last 8 bytes or so in the buffer
<lambda> you're only ever accessing one of the first 256 elements, is that intentional?
<ikskuh> right now: yes
<ikskuh> i have a small part that can read/write framebuffer memory via serial port
<ikskuh> hm
<ikskuh> maybe the writing is broken :D
<ikskuh> is the framebuffer definition correct?
<ikskuh> 15 bits of addresses for 8 bit data?
<lambda> your buffer is 64KiB, not 32, but that shouldn't make much of a difference
<lambda> I think that's how you do arrays in verilog? I'm honestly not sure though
<ikskuh> oh right
<ikskuh> i think i have to run a memtest first :D
<ikskuh> to see if that part is working as expected
<lambda> make sure it doesn't end up being blind to the problem :p
<ikskuh> wdym?
<lambda> it's fairly easy to design a memtest that isn't actually very good at detecting systematic errors
<ikskuh> ah, yeah
<ikskuh> i mean, "write random data to memory, read back, check if it's still the same" should do the trick
<lambda> oh, if you're doing it from the outside, sure - but doing that on device would require an PRNG
<ikskuh> yeah
<ikskuh> okay, so my memory access is borked
<ikskuh> hm
<ikskuh> i feel like that whole RAM thing doesn't work
<gatecat> looking over the backlog, it's not `framebuffer [15:0]` you want but `framebuffer [2**16-1:0]`
<gatecat> it's a set of dimensions; not an address bus width
<ikskuh> gatecat: thanks, i'll try!
<ikskuh> can you explain the difference?
<ikskuh> so
<ikskuh> reg [TOP:BOT] framebuffer [IND_UPPER : IND_LOWER] ?
<lambda> I guess think of it as `reg [WORD_HIGH : WORD_LOW] framebuffer [ARRAY_HIGH : ARRAY_LOW]`
<ikskuh> wow ^^
<ikskuh> consistency \o/
<ikskuh> let's see
<ikskuh> Warning: Replacing memory \fake_ram with list of registers. See src/top.v:151 "oh no"?
<lambda> that's gonna cost you with 64KiB :D
<ikskuh> yep
<ikskuh> "please wait, we're synthesizing your fpga away"
<lambda> there should be some output from memory inference further up detailing why various block RAMs don't work
<ikskuh> ah
<ikskuh> i probably have to enable the verbose output :D
<ikskuh> i only have warnings/errors active right now
<lambda> yeah
<ikskuh> hm
<ikskuh> not much smarter now
<ikskuh> reg [31:0] ram [0:MEM_WORDS-1];
<ikskuh> interesting
<ikskuh> this is from prjtrellis repo
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<ikskuh> huuh
<ikskuh> it looks like the memory_bram pass is never made?
<lambda> what's your script?
<ikskuh> connect_rpc -exec python3 scripts/genpll.py
<ikskuh> synth_ecp5 -top top -json build/top.json
<ikskuh> read -sv src/*.v;
<ikskuh> it looks like theres a wrong order and the brams aren't resolved
<ikskuh> where can i find the synth_ecp5 function/script?
<ikskuh> weird
<ikskuh> i removed my second bram definition
<ikskuh> fixed the first one
<ikskuh> now it seems to not replace it anymroe
<ikskuh> pnr is running now
<tpb> Title: View paste PA4A (at bpa.st)
<ikskuh> seems to do the right thing now
<ikskuh> thanks!
<ikskuh> pnr is still running /o\
<ikskuh> if i build the tools, do i have to pass optimization modes myself or are the toolchains built optimized by default? *thinking*
<lambda> that's alotta luts for a VGA driver
<lambda> what do you mean by optimization modes?
<ikskuh> "-O3" and -"farch=native"
<ikskuh> lambda: that's 32k
<lambda> yosys defaults to -Os
<lambda> nextpnr defaults to -O3
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<ikskuh> hm
<ikskuh> something is wrong
<ikskuh> pnr still running /o\
<ikskuh> lambda: aren't the luts required for interconnect of the RAM?
<lambda> definitely not more than a few of them
<lambda> for read/write enable conversion and such
<ikskuh> hm, weird
<ikskuh> reducing ram size to 256 bytes
<ikskuh> reduced cell count by "yes" :D
<ikskuh> Number of cells: 1474
<ikskuh> synthesis for 256 memory cells works
<ikskuh> i can write them
<ikskuh> Properties: ports=3 bits=65536 rports=2 wports=1 dbits=8 abits=13 words=8192
<ikskuh> this seems to generate all these wires :(
<ikskuh> it seems to generate 2048 rams
<gatecat> it looks like it's mapping to LUTRAM rather than BRAM
<gatecat> what does the code look like ?
<ikskuh> chaotic?
<tpb> Title: View paste ZQAQ (at bpa.st)
<ikskuh> line 88 (transitive 148) is where i read
<ikskuh> and in the process at line 57
<gatecat> so, to map to BRAM, reads must all be in a clocked process
<ikskuh> they are, right?
<ikskuh> or is the rst a problem?
<gatecat> rst is a problem
<ikskuh> ah!
<ikskuh> so synchronous reset is key?
<gatecat> so the current_color_index won't map to BRAM
<gatecat> no reset at all
<gatecat> on the BRAM read port register
<ikskuh> oh
<ikskuh> i can make the reading part into a resetless process, right?
<gatecat> yeah
<gatecat> I'm also not sure if nested 'if's are alright for BRAM reads
<gatecat> they should be but there have been bugs in various tools in the past
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<ikskuh> let's see
<ikskuh> i'm still a learner
<ikskuh> commit, change, let's rock!
<ikskuh> Number of memories: 0
<ikskuh> hm
<ikskuh> should go up, right?
<gatecat> no, that's about unmapped memories
<ikskuh> ah, okay :)
<gatecat> it should never be anything other than 0 post-synthesis, whatever happens, that's memories in the early part Yosys' IL which doesn't include BRAM etc
<gatecat> mapping to BRAM should show "DP16KD" or "PDPW16KD" in the results
<ikskuh> Bram port B1.2 has no sync reset input.
<ikskuh> huh
<Sarayan> what's a reset supposed to do on a memory?
<Sarayan> I know on cyclonev it clears the output latch and nothing else, in particular not the memory contents
<ikskuh> hm, now it complains "Bram port B1.1 has no initial value support."
<gatecat> Sarayan: yeah, if memories have resets they're invariably just for the read latch
<gatecat> but Yosys can't map them yet
<gatecat> ikskuh: remove the `= 5'h00;` in `reg [4:0] vga_b_buf= 5'h00;`
<gatecat> BRAM read ports don't support initialisation in ECP5
<ikskuh> ah
<ikskuh> synthesis is suddenly down to "immediate"
<ikskuh> :D
<ikskuh> DP16KD: 26 / 208 ( 12%)
<ikskuh> this looks good
<gatecat> looks good!
<ikskuh> doesn't work :D
<ikskuh> seems to be stuck on 0x3F
<ikskuh> wait
<ikskuh> okay, this was definitly me being stupid
<ikskuh> memtest seems to run now
<ikskuh> i could hug you right now, gatecat!
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<ikskuh> gatecat, lambda: thanks for the help! you made this possible: https://twitter.com/ikskuh/status/1477756558813585414
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