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<lambda>
ikskuh: very pretty!
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<ikskuh>
thanks :)
<ikskuh>
the cool part is yet to come
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<machinehum>
Hello
<ikskuh>
heya o/
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<chaoticryptidz>
hewwo
<machinehum>
Anyone have an idea as to the feasibility to a USB3 memory controller on iCE40-HX8K? Like something you would find on a USB flash drive?
<machinehum>
Or possibly USB2, I think that's a little more reasonable
<tnt>
USB3 ... not going to happen.
<tnt>
USB2, I don't see any major issues, you're going to need an external PHY for the USB2 High-speed, but implementing some basic usb storage backed by flash seems very doable.
<ikskuh>
yeah, i'd say the same
<ikskuh>
hm, i wonder if it is possible to create raw DVI signals with the ECP5
<ikskuh>
if my calculations are correct, i'd need to emit data with 400 MHz
<ikskuh>
(for 40 MHz pixel clock)
<tnt>
yes. It's been done.
<ikskuh>
uuuh
<ikskuh>
crazy
<ikskuh>
i wanted to use a TFP410PAP for this
<tnt>
Not really. It's not 400 MHz, it's 400 Mbps, so with DDR output it's really only "200 MHz".
<ikskuh>
i have 30 bit per pixel
<ikskuh>
in 3 channels
<ikskuh>
so 10 bits per pixel clock
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<tnt>
yes, but the io register can output on both rising and falling edge of the internal clock.
<ikskuh>
oh
<ikskuh>
i'm a newbie, so i'm still learning things
<ikskuh>
is it legal to run a process with always @ (posedge clk, negedge clk) ?
<tnt>
No
<tnt>
(well .. not if you want it to be synthesizable at least)
<ikskuh>
so how can i do DDR then?
<tnt>
You need to instanciate black boxes blocks that represent the specific ECP5 hardware IO register.
<ikskuh>
ah
<tnt>
ODDRX1F for instance
<ikskuh>
what exactly is that?
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