ChanServ changed the topic of #yosys to: Yosys Open SYnthesis Suite: https://github.com/YosysHQ/yosys/ | Channel logs: https://libera.irclog.whitequark.org/yosys/
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<whitequark> it's unfortunately not a submodule
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<cr1901_> gatecat: Made changes to PR and rebased, should be good to go: https://github.com/YosysHQ/nextpnr/pull/858
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<Guest10> couple of questions about creating rules files for memory_bram
<Guest10> is it possible to define the enable for a port as active low? or is that done during techmap?
<Guest10> how do I define multiple enables for a bram instantiation? I'm trying to at least partially generate nets for use in PCB layout and the last issue I'm having is with RAM/ROM...the device I'm mapping to has an OE, CE, and WE (when it's a ram)...
<Guest10> again, is that during techmap? Or do I need to explicitly create an instantiation in verilog for the ram instead of using logic [7:0] rom[2**13]
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