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02:31
<
marex >
C-o-r-E: uhhhh
02:32
<
marex >
C-o-r-E: nios2 is most likely broken mind you
02:32
<
marex >
doc/arch/nios2.rst
02:33
<
marex >
that is your best chance , I vaguely recall running both u-boot and linux on 10M50 devkit (max10 one), but that needs NIOS2/F core
02:33
<
marex >
the "FAST" one with MMU
02:34
<
C-o-r-E >
marex: thanks, I think i got that part figured out
02:34
<
marex >
C-o-r-E: and I think you need to write the U-Boot to one of the flash memories ?
02:34
<
marex >
probably u-boot.bin to 0xc0000000 or some such ?
02:34
<
marex >
check qsys or whatever it is called now for memory layout
02:34
<
C-o-r-E >
yeah thats what I'm trying to figure out
02:34
<
marex >
C-o-r-E: and check the nios2 core entry point
02:35
<
marex >
C-o-r-E: do you have custom hardware or the 10m50 ?
02:35
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02:35
<
marex >
if the later, download the 10M50 nios2 GHRD , that is what you wanna try
02:35
<
marex >
(btw why nios2 and not e.g. one of the simpler riscv cores with litex?)
02:37
<
C-o-r-E >
marex: where is this GHRD?
02:37
<
marex >
intel website I guess
02:37
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02:38
<
marex >
C-o-r-E: I think in quartus, if you do some "new project" , there is "Access altera webshop thingie" there where you can download reference designs
02:39
<
C-o-r-E >
as for litex, I've seen it online but I'm not knowledgable enough to go there yet
02:39
<
C-o-r-E >
mostly following our FPGA guy's lead
02:41
<
marex >
C-o-r-E: are you looking for softcore ?
02:42
<
marex >
C-o-r-E: for max10 board ? which board do you have ?
02:43
<
C-o-r-E >
i have a 10m50
02:43
<
marex >
C-o-r-E: if all you need is softcore, the rv core which you get out of litex is much easier to synthesise than fighting with nios
02:43
<
marex >
and I am not sure if that board is exactly supported, oh well
02:43
<
C-o-r-E >
I think we actually need to stick with Intel for some IPs
02:44
<
marex >
C-o-r-E: then try to get the 10M50 GHRD with nios2 , it should be in that quartus IP shop
02:44
<
C-o-r-E >
specifically a ethernet MAC with hardware timestamping / PTP
02:44
<
marex >
and then probably use U-Boot version from like 2015ish..2020ish, that might still not be broken
02:44
<
ukky >
C-o-r-E: u-boot.bin has both U-Boot and device tree. You probably should write this one to flash device, unless ypu write your own boot loader.
02:44
<
C-o-r-E >
I think it would be really cool to go the rv route... just maybe another time
02:45
<
marex >
C-o-r-E: btw since litex only generates verilog, you can mix cores from intel and ones generated by migen
02:45
<
C-o-r-E >
going to try and find this "IP shop" thing
02:45
<
marex >
C-o-r-E: File->New project
02:45
<
marex >
C-o-r-E: its somewhere there
02:45
<
C-o-r-E >
ukky: thanks! noted.
02:46
<
ukky >
u-boot-no-dtb.bin has only U-Boot, no device tree.
02:46
<
Forty-Bot >
marex: why is nios broken? no maintainer?
02:47
<
marex >
Forty-Bot: I havent heard from maintainer in a while
02:47
<
Forty-Bot >
a while being 3 years?
02:48
<
marex >
Forty-Bot: yes
02:48
<
marex >
Forty-Bot: too short to call "a while" ?
02:48
<
ukky >
C-o-r-E: u-boot.elf has both U-Boot and device tree, but you need to write your own U-Boot loader to load ELF file from flash
02:49
<
C-o-r-E >
ukky: the vendor has a elf2flash utility so might be the way to go
02:49
<
marex >
ukky: the nios2 jumps to entrypoint in physically mapped memory
02:49
<
marex >
ukky: the core is really simplistic in that way
02:50
<
marex >
C-o-r-E: yes
02:50
<
marex >
C-o-r-E: also look around rocketboards, there may be useful stuff there, even prebuilt binaries
02:51
<
C-o-r-E >
yeah i'm not finding it on the store
02:51
<
C-o-r-E >
i've seen that rocketboards mentions GHRD but didn't find a link
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02:55
<
ukky >
elf2flash, according to Intel, converts ELF to SREC. In my experience, SREC format is about 30% bigger compared to binary program sections in original ELF file.
02:58
<
C-o-r-E >
not sure if the SREC is ending up in flash ulitmately
02:58
<
marex >
C-o-r-E: no, quartus mostly uses ihex
02:58
<
C-o-r-E >
using nios2-flash-programmer with the srec file
03:01
<
marex >
C-o-r-E: I think the qpfl is the full design (or quartus turns it into one)
03:03
<
marex >
Download max10_devkit_ghrd.par file from the attachment. Using the Quartus II software command-line, extract the design files into the host PC:
03:04
<
marex >
C-o-r-E: use that ^
03:06
<
marex >
C-o-r-E: POF is Programmer Object File (stuff that is programmed into flash, either in the FPGA or outside like EPCS/EPCQ)
03:07
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03:07
<
marex >
C-o-r-E: SOF is SRAM object file (you might run into that with max10 too, you can upload bitstream only into the FPGA, not make it permanently stored in the flash iirc)
03:07
<
marex >
C-o-r-E: QAR -- Quartus Archive
03:07
<
marex >
PAR ... some other Archive I guess ... Project maybe
03:08
<
C-o-r-E >
lots of acronyms to learn :O
03:08
<
marex >
C-o-r-E: that rabbit hole is very deep , mind you
03:08
<
C-o-r-E >
indeed! my first FPGA adventure
03:09
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03:11
<
C-o-r-E >
thanks for the help marex! I'll chew on this for a while
03:11
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03:12
<
marex >
C-o-r-E: btw be careful about the quartus version, old quartus projects might flake in new quartus versions, so try to install quartus lite from that era
03:12
<
marex >
unless you have a license for something better obv
03:12
<
marex >
C-o-r-E: feel free to ask if you run into any issues, I actually do have quartus installed and am fiddling with it every once in a while
03:12
<
marex >
but not with nios2, mostly fpga stuff
03:13
<
C-o-r-E >
One problem is that I don't actually have a license to build the IPs like the ethernet MAC
03:14
<
C-o-r-E >
so I might need to get a pre-compiled GHRD
03:21
<
marex >
C-o-r-E: do you know opencores / librecores ?
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03:30
<
marex >
C-o-r-E: at this point I'd probably go for litex , build a soc using that , and possibly wire in the 1588 core by hand, then feed the whole thing into quartus command line interface to compile the stuff
03:30
<
marex >
(litex does generate quartus project + verilog files internally btw)
03:31
<
marex >
oh and btw if you study avalon mm and wishbone interfaces, you might notice significant similarites, just keep the signal polarity in mind
03:38
<
C-o-r-E >
suggestion noted
03:39
<
C-o-r-E >
Heading off for tonight -- ttyl
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16:17
<
sjg1 >
Hmm what happened with the web site? Is there something ready to go live?
16:25
<
f_ >
sjg1: I was quite busy
16:25
<
f_ >
and it's been a long time since I didn't work on Amlogic RE either.
16:26
<
f_ >
I'll work on the website tomorrow hopefully.
16:26
<
f_ >
Today is Amlogic reverse-engineering day :)
16:27
<
f_ >
(also u-boot related)
16:27
<
f_ >
(got SPL to boot things on Amlogic S905, replacing the proprietary BL2, BTW.)
16:32
<
f_ >
"I hope we can get it to at least boot!" we got it to boot :)
16:35
<
sjg1 >
f_: Nice!! I look forward to how this turns out
16:38
<
f_ >
S905 boots already :)
16:39
<
f_ >
Kwiboo helped too!
16:39
<
f_ >
(investigated some issues)
16:41
<
f_ >
I'm working on S905X/GXL now, investigating DRAM init issues at the moment.
16:58
<
f_ >
I'll eventually test it all and send patches upstream so that others can benefit.
17:21
<
sjg1 >
That's really good it hear
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18:41
<
f_ >
sjg1: some great news: I just got DRAM init to work on S905X
18:41
<
f_ >
Now the rest (loading BL31, SCP firmware, U-Boot proper) should be easy.
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19:26
<
marex >
f_: the CC list explains some things :)
19:26
<
marex >
f_: I so wish you success, the less of this blob crap, the better
19:26
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19:29
<
f_ >
S905 and S905X are pretty much done
19:29
<
f_ >
A311D and S905D3 are on todo
19:29
<
f_ >
And I guess that should be about it?
19:29
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20:03
<
f_ >
(which I should rebase at some point)
20:06
<
marex >
f_: I will just add it into reading list and read it when time permits
20:07
<
f_ >
People are mass-donating boards to me lol
20:08
<
f_ >
(exagerating. That said, lvrp16 sent 4 boards to me in total)
20:15
<
lvrp16 >
Boards are cheap, RE is expensive 🤣
20:15
<
f_ >
And I'm offering RE for free lol
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