sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
<drewfustini> I ordered one today as I found it interesting that the SoC is listed as supporting RVA22
<vagrantc> 3
<vagrantc> wek
<vagrantc> gah.
* vagrantc waves :)
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<unlord> is there a canonical way to implement a jump table in rv64?
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<unlord> I'm seeing a lot of beq's
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<clever> unlord: i would assume there is some way to do a load from r0 + (r1*4) ?, but that obviously would need a relocation per entry
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<sorear> for a switch statement, gcc just generates an array access and a jump if the switch is big enough, PIC sticks an add in there and uses relative addresses
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<clever> sorear: ah, so its just implementing the entire LUT and pc-relative in software, easy enough
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<dramforever[m]> maybe this isn't entirely riscv specific but i've always wondered, where the riscv spec says about jalr x1, (x5) and jalr x5, (x1) being "push and pop" for RAS and it says it's for coroutines... what coroutines? i can imagine it working but who's actually using this?
<sorear> I don't think anyone is
<dramforever[m]> not necessarily risc-v, just, who's making coroutines like this
<sorear> given that it's highly unfriendly to procedure calls within the coroutine, i'm guessing this is primarily an assembly thing, maybe s390-ish
<dh`> doesn't make any obvious sense to me
<dramforever[m]> well i can definitely see it working
<dramforever[m]> there should be a way to embed this into a c-like language or something
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