<arkanoid>
hello! I have noob question, please don't assume I have any experience in CPU design and production. Lately I've been reading about digital circuits production pipeline, and I see that VHDL/Verilog/SystemVerilog is the starting point for the major projects. Then I read about RISC-V and how it enables human kind in accessing an efficient cpu architecture without fees. By surfing the riscv github page
<arkanoid>
I don't see any repository containing VHDL/Verilog/SystemVerilog code, I'm curious why
<palmer>
RISC-V doesn't change any of that, it's just an ISA
<palmer>
there are some open source RISC-V cores, but it's kind of orthagonal
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<arkanoid>
palmer: thanks for the answer. Does it mean that RISC-V only shows which instructions the RISC-V CPU should have, and what they should do, without specifying anything about how? No platform-independent, reference/example implementation in VHDL/Verilog/SystemVerilog?
<jrtc27>
RISC-V is just the specification of the architecture, yes
<jrtc27>
there is no official RISC-V microarchitecture
<jrtc27>
there *are* simulators/models though
<jrtc27>
one officially official, one semi-officially official
<jrtc27>
but those are pure software, no HDL involved
<arkanoid>
Isn't it kinda like: here we present what we call CZS - Car Sized Spaceship, it requires rockets to fly and a pointy top and should work like described, here's a plugin for flight simulator 2k to see how it should work. No istructions for example/reference item are provided
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<arkanoid>
my phrase may look like somewhat complaining about something. It is not, I'm just not an english native speaker and I lack the knowledge to understand the full picture. I'm just curious
<Esmil>
I'd say it's more like here is a pdf describing power. 220V +- these limits, 60Hz +- these other limits and the plugs should look like this. Now power companies can compete on producing the cheapest power (chip designers/manufacturors) and all our electric appliances (software) will still work no matter who produces the power.
<dh`>
reference implementations are really for specs where nobody actually expects anyone to build their own (e.g. acpi) or where the spec is a "standard" but it's actually a description of the reference implementation
<dh`>
or sometimes for domains where we don't have enough collective experience writing specs to be able to write something workable without an example
<dh`>
which doesn't apply to ISAs
<arkanoid>
thanks Esmil, dh`
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<gurki>
Esmil: unfortunately the jumpy nature of the riscv ecosystem makes this an impossible task for fabs
<gurki>
you cant just reconfigure your asic if ppl decided that x is the better option
<gurki>
so we kinda need a reference hdl imho
<gurki>
i am fully aware ppl really dont want to give up on having 5000 different cores :>
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