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<Larhzu>
palmer: My first feedback to Zicfisslp went smoothly on GitHub. :-) Thanks again for the encouragement!
<Larhzu>
Now I wonder, will toolchain developers be unhappy if there was a recommendation that all 32-bit instructions that match (inst & 0x0FFF0000) == 0x00170000 should be 4-byte aligned? It's about avoiding accidental landing pads (like endbr64 on x86-64).
<Larhzu>
It matches e.g. "sltiu a4,a4,1" where a compiler can see it and emit ".align 2" but also jal, lui, auipc, or addi/lb/lbu paired with auipc can match. So some of the fixing would need to be done by a linker unless all such instructions would be unconditionally 4-byte aligned.
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<palmer>
Larhzu: Intel was very clever when doing the CFI stuff, I don't think we will be
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<Larhzu>
palmer: Intel was clever, yes. And compilers can avoid accidental endbr64 in immediates, that's clever too.
<Larhzu>
palmer: As long as only 16-bit and 32-bit instructions are present, it's possible to construct landing pads in RISC-V so that accidental landing pads are impossible.
<Larhzu>
One can even have a few bits for landing pad label.
<Larhzu>
Thus my question, how annoying the current draft with the requirement to align certain instructions is.
<Larhzu>
from toolchain point of view
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<palmer>
there's going to be a bunch of issues with CFI from the SW side, we haven't even scratched the surface yet
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<courmisch>
this looks like it'll break the ABI. Arm specifically has a PTE bit to mark which code actually implements landing pads
<courmisch>
otherwise, caboom if you load an "old" shared object into the process
<courmisch>
or is the plan to flag each ELF (like Arm also does) and turn CFI off as soon as one incompatible object is loadee?
<courmisch>
loaded*
<muurkha>
that's an excellent question
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<courmisch>
and in the later case, it will still break JITs
<courmisch>
I guess there is a desire to get this working w/o MMU in which case the Arm strat is unusable
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<palmer>
ya, CFI is going to break the ABI
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<Larhzu>
courmisch: The idea seems to be to turn CFI off for the whole process if one library lacks the flag (or fail to load the lib). No per-page bits.
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<muurkha>
Larhzu: per-page bits is an interesting idea; like, a page could be executable, or executable but only jumpable to landing pad instructions?
<muurkha>
instead of just per-mode
<muurkha>
that seems like it could preserve ABI compatibility
<Larhzu>
muurkha: If I remember correctly, ARM64 does that.
<Larhzu>
Note *if*
<conchuod>
What is the point of an ABI if you don't break it? :)
<muurkha>
heh, well, I sure don't
<muurkha>
conchuod: users
<Larhzu>
Landing pads can be RVI HINTs so in theory one can always use them when compiling.
<conchuod>
Nah, users don't matter. What matters is is edicts from RVI.
<Larhzu>
endbr64 on x86 is such backward compatible no-op too.
<muurkha>
it is
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