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<drewfustini>
If an SoC has fully cache coherent interconnects for all I/O peripherals, then would lack of Svpbmt or Zicbom be a problem?
<drewfustini>
I would have thought the Svpbmt encoding and CMO instructions would not be useful for a fully a coherent system
<drewfustini>
But maybe I am wrong?
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<jrtc27>
no
<jrtc27>
that was the original vision
<jrtc27>
and is what the unleashed and unmatched
<jrtc27>
though once you have PCIe + GPUs you probably do want a way to do write combining
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<bjdooks>
A fully coherent system shouldn't need any cache... I think svpbmt or zicbom alone should be good enough for most cases
<jrtc27>
huh?
<jrtc27>
cache is performance not coherence
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<drewfustini>
jrtc27: thanks
<drewfustini>
> though once you have PCIe + GPUs you probably do want a way to do write combining
<drewfustini>
would it be Svpbmt or Zicbom which would be helpful for that?
<jrtc27>
the former
<jrtc27>
zicbom just lets you work with what you have, not choose how it behaves
<drewfustini>
Ok, thank you
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<geist>
yah trouble is it looks like it's going to create two whole worlds of riscv machines: some that dont have cache coherence instructions/pages, but assume things are cache coherent
<geist>
and ones that act like most arm machines where it's fully manual
<geist>
more headaches for kernel/driver folks
* jedix
looks in just in time for bad news
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