sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
<muurkha> and it's about 0.52 DMIPS/MHz, so a bit under half as fast as the same clock speed Cortex-M0
<muurkha> so, roughly 486 levels of performance? but now you can buy SSDs and lots more RAM for it
<muurkha> also the FPGA probably has enough space for a pretty decent cache
<muurkha> in https://www.eevblog.com/forum/programming/mecrisp-quintus-forth-with-picorv32-on-upduino-and-8-queens-benchmark/ someone seems to have been running a PicoRV32 at 24MHz on a Lattice iCE40UP5K, which seems close to my guess
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<conchuod> bjdooks: crickets
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<bjdooks> conchuod: hah, crickets would be louder
<Tenkawa> fan noise?
<Tenkawa> heheh
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<drewfustini> conchuod: do you know is hardware support needed for the hibernate patches? I had been thinking it was just for JH7110 but now I'm wondering if I should test on the SoCs I have access to
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