sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<drewfustini> Hmm... I just realized that neither Zicbom or Svpbmt are not in the Unpriv and Priv specs on https://riscv.org/technical/specifications/
<drewfustini> I was telling to tell someone evaluating RISC-V that those are ratified, but suddenly I feel crazy because I don't know how to definitely prove it if the Spec section on riscv.org doesn't have it.
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<drewfustini> Thanks, I guess the PDFs linked directly on https://riscv.org/technical/specifications/ are just stale
<dh`> would clearly be good to update them because lots of people will just go fetch specification pdfs and not look at anything else
<dh`> :-|
<muurkha> agreed
<jrtc27> "Specifications for recently ratified extensions, but not yet integrated into the above manuals, are shown on the RISC-V Recently Ratified Extensions wiki page." even appears right on that page...
<jrtc27> but yes it's kind of crap that there aren't newer pdfs there
<muurkha> also I think it's confusing that the current unpriv spec has a date and the previous version has a version number
<jrtc27> hopefully the asciidocification of everything will make it easier to fold these new specs in in future...
<muurkha> because I assumed that the one that didn't have a version number was like a preliminary draft or something
<jrtc27> (though I still don't understand why we couldn't just use latex for everything.. it's far more powerful and doesn't require piles of ruby and javascript)
<muurkha> agreed on latex
<muurkha> also latex will probably be reproducible for longer
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<muurkha> because it's written in TeX82 instead of depending on the whims of how GCC decided to compile whatever version of Ruby for whatever CPU you're using this year
<dh`> I mean, latex is horrible. but everything else seems to be worse
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<muurkha> heh
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<muurkha> and now that we have Jupyter, Wikipedia, and tex.stackexchange.com, latex is a lot less bad than it was
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<drewfustini> update re: 6.4-rc1, I think the issue I saw ("Oops - store (or AMO) access fault [#1]") is something more specific to my environment. I booted 6.4-rc1 with the same config okay this time. The difference is that I am only using busybox initramfs and not trying to mount the ubuntu root fs this time.
<drewfustini> I am leaning towards this not being some systemic issue in 6.4-rc1.
<drmpeg> No problems with 6.4-rc1 on Unmatched here.
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<john_caroll90> Hi! I am currently working on a project making use of PMP in RV32 and am testing in QEMU. Simply put I want to mark a specific memory region (e.g. 0x5000 - 0x6000) as execute only using the 'TOR' mode of PMP. The way I understand the privileged spec is that I have to use two adjacent PMP registers for that, in my case pmp0 and pmp1 where pmp0
<john_caroll90> 'covers' address 0x0 - 0x5000 and pmp1 covers address 0x5000 - 0x6000. This is how I set it up, but it does not seem to be working  and I can still read/write addresses in that range, which implies to me that I am misunderstanding some part of it.
<john_caroll90> The code I am using is the following:
<john_caroll90> li t0, 0x5000
<john_caroll90> csrw pmpaddr0, t0
<john_caroll90> li t0, 0x6000
<john_caroll90> csrw pmpaddr1, t0
<john_caroll90> li t1, 0x0C0F
<john_caroll90> csrw pmpcfg0, t1
<john_caroll90> # Should fail
<john_caroll90> sb t1, -0x20(t0)
<john_caroll90> I've also tried different pmp registers (e.g. pmp4 + pmp5), but to no avail. Thanks in Advance!
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<john_caroll90> I've tried both access in supervisor/user mode and in machine mode (with the lock bit set), but no version seems to work.
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<leah2> anyone have a sipheed lichee yet?
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<muurkha> I got one last year
<muurkha> but all I've done with it so far is plug it in to verify that it powers up okay
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<another|> of
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<leah2> i mean the ones that ship since last week
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<FL4SHK> what is `riscv_mapping_state` in RISC-V's GNU Binutils port?
<FL4SHK> in GAS
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<jim-wilson[m]> mapping state tracks whether we are emitting data or instructions, because sometimes people put data in text sections, the ARM port has the same feature but this happen more often in ARM code than RISC-V code, this info makes the disassembler give more useful output
<FL4SHK> gotcha
<FL4SHK> thanks
<palmer> at some point we were also going to use the mapping symbols for disambiguating conflicting instruction encodings, but that's a pretty RISC-V specific issue
<FL4SHK> gotcha
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