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<bjdooks>
today's warm up is sticking nose into cache management
<bjdooks>
oh hi conchuod
<conchuod>
Heh
<conchuod>
Warm up got a different meaning for each of us!
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<prabhakarlad>
conchuod: thanks. sorry I missed the discussion last night.
<conchuod>
dw chief
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<patersonc[m]>
conchuod: bjdooks : My visionFive2 came yesterday too. To answer your question, there was no shipping notification at all (unless it got lost in junk somewhere)
<conchuod>
Good to know, thanks!
<geertu>
patersonc[m]: Does that mean I might receive one, too? ;-)
<mps>
heh, also I didn't received any shipping notification when I received my visionfive v1 in May
<patersonc[m]>
geertu: That depends on whether you ordered one or not :P
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<geertu>
patersonc[m]: I just knew there was a catch ;-)
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<bjoto>
I guess I was confused: e.g. does make ARCH=riscv CROSS_COMPILE=riscv32-linux-gnu- defconfig build a 32b-kernel (vs rv32_defconfig) And how does clang honor CROSS_COMPILE...
<palmer>
conchuod: I build rv32 kernels with riscv64-*-gcc, that should be ine
<palmer>
pretty sure we just ignore the riscv32-* vs riscv64-* in the Makefiles and always explicitly set the target, that should usually be fine (IIRC there's some host platforms where riscv32-* can't link rv64, it used to be all 32-bit hosts)
<conchuod>
Cool. Should be good so, no need to make any changes to testing stuff so.
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<palmer>
yep, you can pretty much just assume that riscv32-*/riscv64-*/riscv-* is all the same
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<palmer>
I guess if you have non-multilib toolchains then you won't be able to build userspace, but that won't be a problem until selftest
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<enoq>
hi, so I have no clue since I'm not a hardware dev, but the arch to me feels a bit like it could be a clusterfuck to support with all the optional extensions, similar to how ARM has lots of custom code in the kernel
<enoq>
how's that handled with riscv?
<muurkha>
heh, RWT stirred up some skeptics
<enoq>
so all BS?
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<bjdooks>
some of it with alternative, some with specific driver code, etc
<jrtc27>
most of it's just compiler complexity
<jrtc27>
with all the random ISA bits
<jrtc27>
and it's partly tamed by people agreeing on sensible sets to use as a required base
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<jrtc27>
and, one day, official named profiles
<jrtc27>
maybe this'll be the year of profiles
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<enoq>
so tl;dr looks good, will work fine
<jrtc27>
maybe, maybe not, we'll see
<jrtc27>
the current standardised set is rather barebones
<enoq>
so it's in development and too early to tell
<jrtc27>
and profiles should've been defined years ago
<jrtc27>
anyway
<enoq>
I see, thank you for giving me an overview
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<palmer>
IMO i t's a mess
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<conchuod>
I listened to a talk about it. It's going to be great, they said so.