sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<clevis> i'm currently looking at a firmware blob that runs on a t-head e907 core, but there are opcodes from the reserved space in there that don't seem to match any extensions (at least the ones in https://github.com/riscv/riscv-opcodes). do 0xc0e51577, 0xc2c71777 and 0xf0a79577 ring a bell for anyone?
<clevis> the verilog t-head publishes for a number of sibling cores doesn't seem to handle those either. i wonder if the soc vendor messed around in there during integration
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<bjdooks> hmm, trying to make a check on whethre unresolved symbols are actually used isn't really working
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<bjdooks> i think this isn;t going to be easy so probably shelvable
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<cyao> Why is `lb a0,s0,400` giving me a illegal operands error? Am I only allowed to use the pseudoinstruction of `ld`?
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<another|> What do you expect that to do?
<muurkha> we really should switch to a C-subset syntax for assembly languages
<muurkha> t0 = 5;
<muurkha> a1 = *a0;
<muurkha> a1 = a1 + 1;
<muurkha> a2 = a1;
<muurkha> if (a1 != a4) goto 1f;
<muurkha> a1 = *(char*)a3;
<another|> so.... C?
<muurkha> not quite, because you'd still have to have one instruction per line
<muurkha> cyao: maybe you mean lb a0, 400(s0)?
<cyao> Ahh yes! Forgot that the offset is like that! thanks!
<muurkha> happy to help :)
<another|> so... C with arbitrary constraints?
<muurkha> that's definitely one valid way to look at it
<muurkha> assembly is C with arbitrary constraints
<muurkha> but its conventional (01950s) syntax doesn't even express clearly which operands are inputs and which are outputs, and it varies gratuitously from architecture to architecture
<another|> if you want more advanced features, use a higher language like C
<muurkha> I don't want more advanced features
<another|> <muurkha> we really should switch to a C-subset syntax for assembly languages
<another|> <muurkha> a1 = *(char*)a3;
<another|> or write a macro lib in asm
<muurkha> I want the same features, but expressed in a syntax that is more widely understood
<muurkha> I don't think gas's or nasm's macro features are powerful enough to compile `a1 = *(char*)a3;` into `lb a1, (a3)`, especially with decent error reporting
<another|> chars are a higher level structure
<muurkha> on a PDP-10, maybe
<muurkha> but RISC-V is byte-addressable and has `lb` and `sb` instructions
<another|> so.. you want asm with more syntactic sugar. mkay
<muurkha> like every mainstream architecture for the last 40 years
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<muurkha> not even syntactic sugar; you could argue that this is more like syntactic syrup of ipecac, like COBOL's ADD ONE-THING TO ANOTHER-THING GIVING THIRD-THING
<muurkha> and with the same objective, viz., avoiding the kind of needless confusion that was blocking cyao
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<another|> Sounds like syntactic sugar to me
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