sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<HdkR> I noticed in the store-conditional atomic instruction that it doesn't specify if an alignment exception occurs before or after reservation check. Should this be brought up on a ML somewhere?
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<mechaniputer> HdkR: I think after? "The access exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated."
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<mechaniputer> HdkR: "can be". But it doesn't say that it cannot be generated for access that would not be able to complete. It seems unclear to me too. But my guess is that it was supposed to be after.
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<conchuod> I tried to buy a vision five & what came in the post was a "radxa zero" :thinking:
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<mechaniputer> conchuod: From allnet?
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<conchuod> mechaniputer: yessir
<HdkR> mechaniputer: hmm
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<mechaniputer> conchuod: Well, yikes. Hope you don't have a hard time getting them to make things right.
<conchuod> ¯\_(ツ)_/¯ we shall see
<conchuod> I buy stuff like that via paypal for a reason
<HdkR> mechaniputer: Sadly this is in contrast to how AArch64's store reserved work. It does an alignment check before the reservation check. I'll need to change a bunch of logic in my program.
<mechaniputer> HdkR: Well as I said, I'm not certain. Is there a test you'd like me to run on actual hardware?
<mechaniputer> (not that actual hardware is necessarily compliant with the intent of the spec)
<HdkR> Let me start up my PC and spin up a quick test. Should be pretty easy.
<mechaniputer> I think doing the alignment check first is the more natural approach from a hardware perspective. But the spec is not clear to me. Could be either way.
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<HdkR> mechaniputer: Oh, I already wrote this test while I was investigating this, https://gist.github.com/Sonicadvance1/ce91c8b1cad802d9e3ac277376af12a5
<conchuod> palmer: since the window is long open at this point & I've not seen it in next - I assume you're not taking any of my dt stuff this time around?
<palmer> I'm probably taking it
<palmer> I'm just kind of buried right now
<conchuod> heh, that was a quick response
<palmer> (I was like seconds away from sending this PR...)
<conchuod> before I could say "none of it is important, so its no big deal"
<conchuod> Ye figured you were buried palmer so not bothered, more curious :)
<palmer> thanks
<conchuod> I'm 50% of the way there on key signatures to make it easier next time around (:
<mechaniputer> HdkR: Segfault. https://termbin.com/vsdj
<HdkR> mechaniputer: hit c, it should do two
<palmer> conchuod: awesome ;)
<palmer> I just sent the PR, I want to base the rest of this post-merge so I'm going to go do some work stuff for a bit
<mechaniputer> HdkR: https://termbin.com/eshb
<HdkR> mechaniputer: oh, that's interesting. Before the c can you do `disas $pc,+4` each time to confirm?
<HdkR> Should land directly on lr then sc on each fault
<conchuod> palmer: ye as I said, nothing "important" so kick the can as much as you want.
<palmer> I'd still like to take the stuff, though -- bad to delay just because I'm busy
<mechaniputer> HdkR: https://termbin.com/4lxx
<HdkR> mechaniputer: Nice! That confirms mismatched behaviour between your hardware and qemu
<mechaniputer> HdkR: Alright. This is a VisionFive V1 with U74 cores, running Debian with clang 13.
<dh`> ....why would you ever do a faulting unaligned access on purpose with SC?
<HdkR> This is a reduced test case so you can't really see the reasoning. Larger use case is emulating unaligned atomics in a signal handler.
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<dh`> ah hmm
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<HdkR> I could wait for ZAM, but need to run on non-ZAM hardware as well. Also qemu doesn't support ZAM either :P
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