sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<muurkha> interesting, https://news.ycombinator.com/item?id=31244786 says, "At the lower end [RISC-V cores] have a big advantage as they can reach similar performance as Arm at half the silicon which translates into 4x lower price at similar volume of production." I didn't know that!
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<conordooley> geertu, I gave the reset controller a go - if I link a branch later would you be able to take a look and see if it is sane?
<qwestion> do irc xmpp matrix apps work on rv, particularly vision 5?
<geertu> conordooley: sure
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<conchuod> geertu: thanks! don't have a k.org account yet so will have to be github: https://github.com/ConchuOD/linux/commits/mpfs-reset
<geertu> conchuod: Thx, will have a look later...
<conchuod> No rush, you're doing me a favour :)
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<muurkha> palmer: do you know if the XuanTie designs (or anybody else) are doing more aggressive macro-op fusion than the one-instruction jump case where the SiFive 7-series does it?
<palmer> Don't know anything about the XuanTie cores, but the Ventana guys had a patch (though not really clear if there's HW)