sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<Jmabsd> Hi all! Just curious, do you believe there will be any faster RISCV with PCIe, than the SiFive Unmatched, anytime soon - when do you expect the next one really? Smaller litography and support for out of order execution would accomplish this
<Jmabsd> (_whitelogger,abelvesa,ats,carlosedp,crest,dh`,geist,jcm,rjek,sorear,zaps_: your great insight would be much appreciated;apologies for ping)
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<Jmabsd> palmer1: hi
<dh`> why me? I do software
<Jmabsd> apologies for the pinging
<Jmabsd> i saw an announcement that SiFive will make some faster CPU next year using PCIe logics from Intel erh
<Jmabsd> the SiFive is a great historical achievement as it's a fully fledged computer. however it has no Out of Order Execution
<pierce> I thought this chat room was compromised for a minute
<Jmabsd> =o ?
<Jmabsd> ..and the SiFive board is is it.. 28nm, 22nm
<pierce> Google is your friend, my friend
<Jmabsd> and 256GB of virtual memory. so it's a stellar baseline computing environment however it is not yet competing in performance, neither with laptops nor with Pi 4 (BCM2711) / ARM72
<Jmabsd> SiFive did announce that they manufactured their first 5nm CPU this May, however that was internal
<Jmabsd> Intel Horse Creek using a SiFive core to be released in 1-2 years. 7nm. https://www.tomshardware.com/news/intel-to-adopt-sifives-new-high-performance-p550-risc-v-cores
<Jmabsd> Because it's Intel, it automatically becomes less interesting, heh.
<Jmabsd> pierce: are there any more RISCV devices coming out with PCI interface, anytime soon?
<pierce> ¯_(ツ)_/¯
<pierce> I know as much as you do
<pierce> I don't work for any RISC-V related company, and I only know what has been publically announced
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<pierce> I don't think you'll find anymore information here about upcoming boards or chips than what you can find on Google
<pierce> I'm sorry but this chat isn't where you get inside goss on internal matters
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<pierce> You may have better luck here http://risc-v-international.slack.com/
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<Jmabsd> pierce: sure i totally see there is no extra info here. just thought i may have missed something
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<Jmabsd2> pierce: the Slack you mentioned is it invite-only?
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<Jmabsd2> Ah, the invite link to Slack is here https://riscv.org/technical/technical-forums/
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<Jmabsd2> pierce: apart from that Intel Horse Creek, are you aware of any more upcoming RISCV64 with PCI?
<Jmabsd2> none of the RISCV SBC:s in the pipe, have PCI. they're really low-end. so SiFive Unmatched appears to be the highest end RISCV until 2022-2023 and then that Intel thing would come
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<Jmabsd2> ok i googled around a bit. the SiFive Unmatched is still a bit slower than a Raspberry Pi 4. There are no interesting news circulating in this moment for upcoming 2022 releases.
<Jmabsd2> The V8 Javascript engine was ported to RISCV just recently, great
<Jmabsd2> The V8 port is "for any RISC-V ISA that supports RV64I, M, A, F, D and Zifencei extensions". Just curious, does the U74 (unmatched) have them?
<Jmabsd2> pierce,*: ? ^
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<AhmedCharles[m]> Yes, it's rv64imafdc+Zifencei, with perhaps a few others.
<AhmedCharles[m]> Though, it's weird, I'm not sure how you're supposed to list the Z instructions.
<AhmedCharles[m]> Ah, so the U74 cores are rv64gc and the spec says: We have also defined an abbreviation “G” to represent the “IMAFDZicsr Zifencei” base and extensions,
<AhmedCharles[m]> as this is intended to represent our standard general-purpose ISA.
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<Jmabsd> AhmedCharles[m]: Thanks a lot for the insights!! Curious where is there a spec document that says that SiFive U74 supports those said extensions???
<Jmabsd> Also just curious, this means that Chrome with that RISCV-supporting V8 Javascript engine will just simply build and work out of the box right? If so, neat!
<jrtc27> https://www.sifive.com/boards/hifive-unmatched and take your pick of the product brief, datasheet and fu740 manual
<jrtc27> it's not hard to find
<Jmabsd> ah, i looked at the fu74 page. obv look at the SBC's page. good. thanks.
<Jmabsd> jrtc27: so these are just totally conventional extensions, this means running that Chrome with that V8 Javascript engine should just work out of the box right - this is totally uncontroversia
<Jmabsd> l
<Jmabsd> most mundane typical class of CPU ops
<jrtc27> the U74 page only has the abbreviated form (because that's really intended for vendors who know about RISC-V so they really should know what G means) but the manual linked on that page does list the extensions in full
<jrtc27> yes, not having any of those extensions on a linux system would be noteworthy and a bad idea
<jrtc27> floating-point is about the only one you could conceivably leave out for some use cases
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<Jmabsd> jrtc27,AhmedCharles[m]: one more question - the U74 in SiFive Unmatched, does it have any meaningful virtualization support?
<jrtc27> no
<Jmabsd> i talked to someone who should be an expert and he said the hardware does *not* support virtualization
<Jmabsd> mhm ic.
<jrtc27> that's the H extension, which is not yet ratified
<Jmabsd> so because it wasn't ratified, SiFive didn't make any silicon for it yet - i see.
<Jmabsd> There is a Linux KVM RISCV fork. does it work on any real world hardware? ha ha
<jrtc27> the Rocket design has H support
<jrtc27> people have used that on FPGA for testing
<jrtc27> (as well as QEMU)
<Jmabsd> cool! aha but, it's not in the silicon on the SiFive Unmatched U74. I see. thanks for confirming!
<Jmabsd> jrtc27: last question, are you aware of any other high/higher-performance RISCV64 chip on the way currently? (Apart from that Intel Horse)
<jrtc27> the SiFive cores, which Intel said they want to use in their Horse Creek, are all I know of
<jrtc27> in the general-purpose space
<jrtc27> Esperanto have their $many core AI/ML HPC thing
<jrtc27> and presumably Alibaba/T-HEAD are working on their next generation of cores
<Jmabsd> jrtc27: cool! Esperanto, are they fast enough, could one run a normal OS on it? also same with Alibaba/T-HEAD, may those become available on the general market
<Jmabsd> i recall reading the news that the guy who was chief architect for Sun/Oracle's SPARC CPU:s, started a RISCV business, but I have not heard anything more from them since.
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<jrtc27> most of the cores are really just compute units for accelerating AI/ML workloads
<jrtc27> I highly doubt they have anything other than M-mode or M-mode+U-mode
<jrtc27> supporting virtual memory would be silly
<jrtc27> but the SoC does have four general-purpose OS-capable cores on it to manage the thing
<jrtc27> (1088 accelerator cores and 4 general-purpose cores per SoC)
<sorear> Jmabsd: pinging a ton of people like that is considered rude in a non-emergency
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<sorear> Jmabsd: regarding your actual question commercial chipmakers are about as secretive as militaries and nobody who actually knows anything will be able to answer
<pierce> Is this what I sound like? Questions that have no purpose. Questions that are way too premature. Questions that are very Google-able?
<Jmabsd> pierce: i liked to understand where RISCV is at now. the reference hardware is the Unmatched. i did not know what questions are premature.
<Jmabsd> google is nice for indication but still
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<Jmabsd> (sorear: sorry)
<Jmabsd> sorear: your allegory is good.
<Jmabsd> thanks all for helping me understand this space currently. interesting that Unmatched is indeed.. unmatched! lol
<Jmabsd> the 16GB RAM is very helpful. that plus incredible IO counterweight its CPU speed which is not very great. i guess the L2 cache of 2MB helps a bit too.
<Jmabsd> its performance should approximate a 4-core high-end desktop computer of approx year 2008, 2006? :-)
<Jmabsd> ok here off
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<GenTooMan> sorear, no one wants to be a target as they say.
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<dh`> I'm just curious what prompted them to pick 11 people to ping
<sorear> they pinged everyone in the OFTC channel
<dh`> I suppose probably it was just the first line of people in the names list
<dh`> (on whatever server they were on)
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<meowray> jrtc27: is your setup -DBUILD_SHARED_LIBS=on or -DLLVM_LINK_LLVM_DYLIB=on ?
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<jrtc27> -DBUILD_SHARED_LIBS=ON
<jrtc27> (along with split dwarf and gold)
<jrtc27> (Ubuntu 18.04's LLD is too old to be useful...)
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<meowray> similar to mine. added a comment https://reviews.llvm.org/D109192#2984321
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<jrtc27> I thought it was a fairly common setup...
<jrtc27> think it might even be documented as a suggested way to get faster dev builds
* jrtc27 discovers https://llvm.org/docs/Packaging.html from the before-CMake times
<meowray> llvm/docs "BUILD_SHARED_LIBS is only recommended for use by LLVM developers"
<jrtc27> yeah I'm aware of that much :)
<jrtc27> actively discouraged for distros
<meowray> from a bystander: your words likely aggravated compnerd...
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