<somlo>
this, while theoretically a race, ensures that everyone spins on that while the boot core does its thing, before finally writing a 1 there to let everyone know it's safe to jump into bbl
<somlo>
so that's probably *not* the part that's stopping it from working...
<jrtc27>
yeah that's wrong but hard to lose that race
<jrtc27>
putting the variable in .data is the correct way to do that
<jrtc27>
to me it looks like you might just not have built your kernel as SMP
<somlo>
jrtc27: now *that* would be stupid on my part, and entirely possible :D
<somlo>
let me check and make sure
<jrtc27>
"Invalid cpuid for hartid" means riscv_hartid_to_cpuid returned < 0 but, unless you've managed to get negative cpuids from somewhere, that will give an error in the implementation of riscv_hartid_to_cpuid when it fails to find a hart
<jrtc27>
*except* for UP kernels where there's a different simpler stub
<sorear>
it's not a terrible formulation but the entire thread ignores that that's what risc-v has been doing the entire time through the extensions system
<sorear>
once again, the biggest mistake was calling it "risc" because people think they know what that means based on oversimplified explanations of 1980s market trends
<sorear>
(arguably it is what ALL "risc"s have been doing since the beginning)
<solrize>
bah x86 extensions are a huge mess even when they're only coming from one vendor. come up with 3 or so profiles and be done with it
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<sorear>
it'd be nice but I think there's a natural equilibrium here, you have an N billion dollar market and people spend N/k billion on inventing incompatible micro-optimizations for small k :(
<drmpeg>
Heh, when I moved from 8080 to 8086, I thought that REP MOVSB (and MOVSW) was the best instruction ever invented.
<drmpeg>
That was when I lived in Bedrock and drove a foot powered car with two stone wheels.
<sorear>
would it have been that difficult for them to make it 2 bus cycles per byte copied?
<sorear>
/weird extremely retrospective wondering
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<rvalles>
drmpeg: Imagine using a 68000 :P
<jemarch>
I learned assembler with a 68000
<rvalles>
I've only learned 8086's painfulness recently (optromloader).
<rvalles>
it's pure suffering relative to m68k which is joy.
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<rvalles>
jemarch: :)
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<rvalles>
so few registers, some are 8/8 or 16, some are only 16. Then among these many groups of instructions are restricted to some register or another.
<rvalles>
And then there's of course the madness which is segments.
<rvalles>
that relative to the nice 32bit isa m68k had, with so many GPRs and address registers :)
<jemarch>
the 68000 had very nice peripheral chips
<jemarch>
the interrup controller
<drmpeg>
Somehow I missed 68000. After 8086/186, I moved to i960.
<drmpeg>
I also worked with a fully custom RISC chip at C-Cube Microsystems.
<drmpeg>
It was a bizarre architecture with some 36-bit registers. The weirdest part was that the instruction cache had to me manually loaded.
<drmpeg>
be manually loaded.
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<drmpeg>
The C compiler (some early version of gcc) had a trap of some sort. When you fell of the beginning or end of the I-cache, it would load the next page.
<drmpeg>
It was an MPEG-2 encoder chip. It took a dozen chips in parallel to do 720x480.
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* gordonDrogon
has avoided x86 and plans to continue to do so for ever...
<gordonDrogon>
closest was 8085 ...
<gordonDrogon>
never experienced 68K either but mostly because I never had a reason to back in it's day...
<gordonDrogon>
i960? Interesting. I did a lot with the i860 and its dual instruction mode.
<drmpeg>
Les Kohn (the designer of the i860) ended up at C-Cube. He transformed that 12 chip monster down to one chip.
<drmpeg>
Using SPARC.
<geertu>
gordonDrogon: i860 an i960 are totally different
* gordonDrogon
nods. I know. so many different cpus from the same maker.
<drmpeg>
I never got a chance to work with him. I consulted there from 1993 to 1995 and finally became an employee in 1999 (perfectly bracketing his time there).
<gordonDrogon>
I liked sparc though - we used the i860 more or less as a stop-gap before developing a sparc system.
<pierce>
How come this isn't more of a widespread issue?
<drmpeg>
Ubuntu patches gcc to always include libatomic.
<drmpeg>
Or Debian I guess.
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<jimwilson_>
RISC-V is the only major gcc target that doesn't open code sub-word atomics, so is the only major target that requires -latomic, and I think most OSes have a workaround now to link with libatomic always
<rvalles>
jemarch | the 68000 had very nice peripheral chips --> never played with the motorola peripherals, only the Amiga.
<rvalles>
(incidentally, check out AmigaXfer if you own an Amiga)
<drmpeg>
Actually, they're patching CMake to always include -latomic
<drmpeg>
If you build CMake from source on Unmatched, you will have the libatomic problem.
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<jrtc27>
only watching the LPC livestream on youtube but: correction - that *is* implemented, but only for LLVM
<jrtc27>
as __attribute__((__target__())) maps directly to target features
<jrtc27>
so you can already write __attribute__((__target__("v"))) with LLVM today (provided you use the integrated assembler, which side-steps the .option arch issue, and provided you have some way to actually determine whether to use that function or not)
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<palmer1>
sorry, I forgot LLVM had this -- and I guess there's too many chats going on
<jrtc27>
I should perhaps have registered
<jrtc27>
but oh well
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<drewfustini_>
For those interested in the RISC-V Microconference that happened to today at Linux Plumbers, here are my notes
<yyp>
Hi! Are there any good resources on virtual memory management on RISC-V from OS' perspective? The privileged specification was a bit unhelpful to me
<jrtc27>
do you understand how paging and virtual memory work in general?
<jrtc27>
ignoring the exact implementation details for a specific ISA like x86, AArch64 or RISC-V
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<yyp>
Somewhat
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<yyp>
I'm intereseted more in exact implementation details, like how do I get the root page or find a new one
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<jrtc27>
define "root page", "get" and "find a new one"
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<jrtc27>
because those all sound to me like things you tell the hardware about, not things the hardware tells you about
<jrtc27>
all of which are also generally independent of the ISA
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<jrtc27>
(you have a page allocator somewhere in your kernel that you allocate page table pages from, and you need space in your process info struct to store a pointer to the root of that process's page table so you can switch to it on context switch *anyway* so you just always look at that rather than getting the page number out of the hardware and reconstructing a pointer)
<jrtc27>
so it feels to me like you still should be looking at higher-level details than "how it's done on RISC-V"
<jrtc27>
as your question suggests you don't have a good grasp of that
<jrtc27>
(and generally once one does have a good grasp of that, reading the privileged spec and mapping it onto the exact ISA features RISC-V provides is pretty straightforward)
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<yyp>
Got it
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