sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<geist> The atomic mechanism probably relies on a cache line being marked exclusive to the cpu as its doing it
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<sorear> the A stands for atomics
<sorear> if you have A or C, you can use amos. if C it works as geist describes, otherwise if A the amo itself is put on the bus for the device to deal with. not all devices support that
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<geist> yah i was surprised to see that you can do atomics on hw registers in the sifive embedded (and probably non) hardware. nothing in ARM land i've ever seen supports atomics to hardware like that
<geist> possibly an artifact of whatever bus sifive is using there
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<somlo> geist, sorear: thanks, that makes sense now
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<sorear> writing on the wall for nios?
<gatecat> and vendor softcores in general - Lattice have pretty much ditched lm32 for riscv, too
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<xentrac> it's had to justify rolling your own now, yeah
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