sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<dh`> I've also had this misfortune, because I used elm as my mailer for a long time
<dh`> (re pascal, all I had in mind was C extension/Pascal extension, joke if you can call it such was no deeper than that)
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<xentrac> ohh
<xentrac> haha
<xentrac> why thumb is not my favorite instruction set
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<solrize> thumb is the thalidomide baby of instruction sets?
<GreaseMonkey> there's thumb-2 which is basically compressed traditional ARM, and then there's thumb-1 which is basically "ARM minus fun"
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<pabs3> "Apple Exploring RISC-V, Hiring RISC-V 'High Performance' Programmers"
<pierce> Bit late pabs 😅
<pabs3> ah, woops
<pierce> All good, I just wonder who picked it up first
* pabs3 wonders if they will ditch arm
<mps> apple M1 with riscv ;)
<pierce> It was discussed somewhere that it's likely to start with microcontrollers
<pierce> Maybe in the T1 chip
<mps> swarm of microcontrolles?
* mps desperatelly want notebook with riscv
<pierce> I'm just hoping Microsoft at least starts adding RISC-V support to Visual Studio (Code)
<pierce> mps: I satiated my desire for a RISC-V notebook by getting one of these https://www.aliexpress.com/item/1005001761528858.html
<pierce> And hooked it up to my D1
<mps> pierce: interesting idea
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<jrtc27> pierce: good luck running an upstream linux kernel on the D1 any time soon...
<pierce> Lol I know
<pierce> There's a telegram "dedicated" to the mainling for D1. JTAG doesn't even work
<pierce> And something about the jh7100 not supporting debug?
<jrtc27> I mean it's their own damn fault for not doing coherent DMA
<pierce> Real shame
<pierce> I just use the board in a "higher level" and use it for porting applications
<pierce> I truly wish I had the chops most of you all have and do lower level things that end up in the kernel
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<mps> I've created small and simple script to run rv64 alpine linux under qemu on x86_64 host here https://arvanta.net/alpine/install-alpine-riscv64-qemu-uboot/
<mps> my small contribution for riscv
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<mps> clandmeter: ^ :)
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<pierce> mps, I'd love you forever if you can get a debian image running under qemu with 3d accelleration
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<dibi58> anybody knows anything about the nezha board ?
<pierce> You will need qemu 6.1 though
<mps> pierce: I'm long time debian user but now I'm retired from debian
<mps> yes, on alpine edge we run qemu 6.1.0
<mps> I could try next week to run it with virtio-gpu and see will it work
<pierce> My love is off the table I'm afraid
<pierce> mps: Yeah apparently I need to recompile the kernel?
<pierce> For the host and guest?
<mps> pierce: I'm not sure for debian but host kernel should work without recompiling
<mps> for guest it is good idea to use 5.14.x
<mps> you can look at alpine kernel config for virt flavor here https://git.alpinelinux.org/aports/tree/community/linux-edge/config-edge-virt.riscv64
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<jrtc27> dibi58: define knows
<dibi58> status, where to buy if available
<jrtc27> it exists, upstream kernel support isn't happening any time soon due to its lack of coherent DMA, don't know now the indiegogo campaign is closed
<palmer1> we're trying to work through how to deal with the D1 upstream, they've recently published some docs which was the big blocker but I haven't had time to look at them
<jrtc27> would be interesting to see what you end up doing..
<jrtc27> all I've seen so far is an incoherent flip-flopping stream of patches that don't learn from feedback
<palmer1> the implementations have all been a mess, but the rough plan is to implement the standard non-coherent stuff and then describe whatever the D1 is doing as errata against that
<palmer1> then there'll at least be some sanity to the process
<jrtc27> ok, that kinda makes sense if it can be made to fit
<jrtc27> do their cmo's at least look like normal-ish ones?
* jrtc27 won't be racing to implement this in FreeBSD though...
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<palmer1> doesn't really matter that much, the flush interface is really simple
<palmer1> it's more about sorting out what semantics the arch/riscv primitives have, and then using a big hammer to make the D1 stuff fit that
<jrtc27> ack
<palmer1> if we do it the other way around we'll start to have a bunch of code that depends on the D1 way of doing things, and it'll be a headache to untangle that for the future stuff
<jrtc27> yeah no that's not a good idea and also sets a bad precedent
<jrtc27> similarly with the vector mess...
<palmer1> that's a whole different problem -- at least for the V stuff they were sort of trying to play by the rules
<jrtc27> the similarly was referring to precedent
<jrtc27> and ehhh not really
<jrtc27> it was a draft standard, but it was clearly something that you shouldn't implement
<jrtc27> anyway
<palmer1> there was a lot put out by the RISC-V folks saying that it should be implemented
<jrtc27> hm, guess there's some backstory I wasn't aware of
<palmer1> likely ;)
<jrtc27> probably for the best
<jrtc27> I only get involved with internal politics stuff when I feel it's impeding technical progress..
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<jimwilson> nezha is available from aliexpress.com
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<jimwilson> drafts were supposed to be implemented to get experience to improve the next iteration, but they weren't supposed to be implemented in SoCs, they were only supposed to be experimental designs to simulate or put on FPGAs
<dh`> if implementors don't look at drafts, they don't progress beyond drafts :-)
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<dibi58> @imwilson thank you, found them, may check one out one of these days
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