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* gordonDrogon
wonders if anyone here has implemented RISC-V on the Cmod-A7 device? I've seen some "how to's" but just wondering if anyone has any first-hand hints and/or tips, or even just a "yea, works fine" sort of thing ...
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<geist>
hmm, looks like the cmod-a7 is an artix 35klut device
<geist>
no reason that couldn't punch out a sizable riscv core (or more than one)
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<palmer1>
geist: I'm not really an FPGA guy, but assuming that's the a7-35t then it should be pretty straight-forward to put a RISC-V core on it but if you're looking for more than one or a lot of peripherals you'll need an FPGA-optimized hardware stack
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<gordonDrogon>
thanks - just playing with ideas - and yes, the -35t unit and maye even squeeze a VGA output on it too using the internal block ram.
<gordonDrogon>
the 32-bit core with hardware mul/div is all I'm after - for now, anyway.
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<geist>
yah based on past experience with punching out 32bit cores it should fit really easily
<geist>
but as palmer1 says the peripherals you want may add enough
<palmer1>
if you've got an FPGA-optimized system then just a 32-bit core should be easy and as long as it has a way to turn down the mul/div unit you should be fine
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<gordonDrogon>
it's new ground for me - essentially I want RISC-V, some GPIO like SPI to external storage, blinkenlights, and if at all possible VGA video output.
<gordonDrogon>
I don't need (not want) the "IoT" stuff on other small boards and a big board that can run Linux is way OTT. This is what I'm looking at:
<somlo>
what is the expectation for SMP harts' state (specifically, I have a 4-core 64-bit Rocket) right before entering BBL? Is it the same as for SMP linux (where they are expected to jump to the entry point at the same time, with a0 containing the hart id)? I.e., what should the bootcode/bios do on SMP right before entering BBL?
<palmer1>
somlo: there's nothing in RISC-V for that, it's up to the SOC vendor
<palmer1>
essentially anything goes in M-mode
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<somlo>
palmer1: thanks! I'm using LiteX with the Rocket Chip (https://github.com/litex-hub/linux-on-litex-rocket), and I'm trying to write the LiteX bios bits that load and launch a BBL blob which contains an embedded DT and Linux kernel image
<somlo>
so I'm trying to figure out how to line up four Rocket harts so they end up doing the right thing when entering BBL, after the blob is loaded (e.g. from sdcard or over tftp)
<palmer1>
is there a reason you can't just use opensbi?
<somlo>
the only way my fpga (nexys4ddr) has enough room for more than one hart is if I leave out the FPU; I know BBL does fpu emulation in M-mode, and opensbi did not, last time I checked
<palmer1>
can't you just run a rv64imac system?
<jrtc27>
to answer your earlier question, bbl and opensbi both expect all harts to just jump to the entry point
<jrtc27>
(which is *not* the case for linux/freebsd any more, recent sbi specs have a more sophisticated approach of having the OS ask for other harts to start at a given address)
<jrtc27>
with a0=mhartid a1=dtb
<somlo>
so right now I have non-zero-hartID cores spin while the bios loads a blob into main ram, then everyone jumps to the blob (bbl) start with a0 set to the hart id and a1 set to 0 (bbl has a compiled-in DTB and vmlinux)
<somlo>
symptom is linux boots, but only hart 3 is available; getting PLIC and hart init errors during boot for the other harts
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<somlo>
if I'm lucky, I screwed something up in the DTS I use with BBL (had to adapt it from what Rocket's chisel elaboration generates automatically, might have missed something)
<jrtc27>
if you upload it somewhere I can take a look
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