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<hendursaga>
Jmabsd: open-source as in, source-available?
<Jmabsd>
hendursaga: I think so :(
<Jmabsd>
i got this from a veeery reputable source however you please doublecheck. for RISCV it's imperative that boot code is open source.
<sorear>
not sure what the source is but calling sifive “the main vendor” doesn’t bode well for their credibility
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<jrtc27>
open boot code is not imperative
<jrtc27>
if the hardware's not open why does it matter the boot code isn't
<sorear>
andes has waaaaay more design wins
<jrtc27>
and an IP company like SiFive isn't going to be putting their cores out for free
<jrtc27>
sure I'd *rather* firmware were but at the end of the day it's a bit meaningless to draw the line at firmware but not hardware
<xentrac>
firmware can typically be backdoored after the fact, hardware can't
<xentrac>
firmware can't either if your ROM isn't in-system-programmable, but nowadays they usually are
<xentrac>
the case of the PS3 is instructive: the OtherOS feature that allowed you to boot Linux on them was a selling point, but at some point Sony decided it was enabling cheating, so they offered a firmware upgrade that removed OtherOS
<xentrac>
then they banned you from playing online if you didn't install the upgrade
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<jrtc27>
just because something is open doesn't mean you can build your won
<jrtc27>
*own
<jrtc27>
could be BSD-licensed but required to be signed by a private key
<xentrac>
(non-upgradable firmware would have prevented that attack, while open-source firmware wouldn't)
<jrtc27>
having firmware be replaceable opens up the ability to put open firmware on it in future
<jrtc27>
but also opens it up for abuse
<jrtc27>
there is no right answer
<jrtc27>
and as a result I personally strongly disagree with the FSF stance that firmware blobs are fine so long as you cripple the hardware by making it forever read-only
<jrtc27>
the ps3 case is a bit unusual
<xentrac>
I think it's not that important to put open firmware on it, unless the original firmware has security holes you want to close
<jimwilson>
the SiFive Unleashed/Unmatched FSBL is open source
<xentrac>
or unless it prevents you from running the software you want, like locked bootloaders on cellphones
<jimwilson>
I think some other parts have non-open source bootloaders, but they are embedded devices that can't run linux/freebsd, so I don't care
<jrtc27>
jimwilson: I assume in this case Jmabsd is talking about the ZSBL which was open for the unleashed but I believe isn't for the unmatched (at least not currently)?
<jrtc27>
not that it does much of interest
<xentrac>
they could surely run FreeRTOS
<dh`>
making firmware not open in the interests of 'security' is just obscurity
<jrtc27>
presumably there are about 20 different Arm-M cores on the board :)
<Jmabsd>
sorear: "andes" = ?
<dh`>
whether it's attempting to hide bugs in the firmware or bugs in the hardwae
<xentrac>
concur
<sorear>
Jmabsd: search for “andes riscv”
<Jmabsd>
sorear: Interesting, Andes is another RISC-V core implementation aside from SiFive? cool
<xentrac>
there are lots
<jimwilson>
a device like the Dr Who hifive inventor can't run much of anything other than toy programs
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<Jmabsd>
Sorry last I saw was <jimwilson> a device like the Dr Who hifive inventor can't run much of anything other than toy programs
<Jmabsd>
I wrote: sorear: what are Andes' design wins over SiFive's designs? , > and as a result I personally strongly disagree with the FSF stance that firmware blobs are fine so long as you cripple the hardware by making it forever read-only
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<Jmabsd>
sigh two disconnects
<Jmabsd>
Sorry last I saw was <jimwilson> a device like the Dr Who hifive inventor can't run much of anything other than toy programs
<Jmabsd>
I wrote: sorear: what are Andes' design wins over SiFive's designs? , > and as a result I personally strongly disagree with the FSF stance that firmware blobs are fine so long as you cripple the hardware by making it forever read-only
<Jmabsd>
jrtc27: Oh that's odd , jimwilson: what is FSBL an abbreviation for and what is the URL , dh`: agreed , Can one buy an Andes RISCV64 for money?
<jrtc27>
First Stage Boot Loader, and it's OpenSBI+U-Boot
<xentrac>
01:10 < sorear> none of that is correct
<xentrac>
01:11 < sorear> andes and sifive are *companies*
<sorear>
Jmabsd: the "ZSBL" is 4 instructions, AFAIK it doesn't have "source code" because it was written directly in binary form
<xentrac>
heh
<Jmabsd>
sorear: wow, okay! Well in this case, the statement that the SiFive boot code is closed-source is absolutely incorrect???
<jrtc27>
nah it does a bit more than that
<jrtc27>
it looks at MSEL, scans the device for the U-Boot SPL partition and reads that
<jrtc27>
see §6.2 of the FU740-C000 Manual
<xentrac>
cool, thanks!
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<sorear>
the andes press releases very carefully dance around the question of whether they've shipped anything
<sorear>
i would caution against becoming emotionally invested in any way in sifive's non-mass-production demo chips
<Jmabsd>
sorear: emotionally invested -> why?? :)
<sorear>
because statistically they don't exist
<jimwilson>
SiFive is an IP core company like ARM, if you want an ARM SoC, you don't buy it from ARM, you buy it from a hardware company that is an ARM customer like Samsung or Qualcomm, similarly, you should not expect RISC-V SoCs to come from SiFive but rather SiFive customers, but the market isn't there yet, so we have non-mass-production demo chips to try to jump start the market
<jimwilson>
I think the Allwinner D1 is mass production, but it has lots of differences from the standard RISC-V ISA
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<GenTooMan>
jimwilson, well everyone has a desire to change stuff sometimes to make a name for themselves, sometimes they aren't thinking clearly, sometimes it's a suggestion. Just because you can do something doesn't mean you should. My thinking.
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<Jmabsd>
jimwilson: oh just curious how is hte Allwinner D1 different from the ISA
<sorear>
Jmabsd: nowhere in that does it say their licensees have shipped a single *riscv* chip
<sorear>
it does say they have riscv revenue, but that could happen in advance of shipping
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<jimwilson>
the andes page says most of them are NDS32 ISA chips, aka Andes V3 chips
<jimwilson>
allwinner D1 has draft V incompatible with standard V, draft B incompatible with standard V, draft non-coherent cache support incompatible with standard non-coherent cache support, plus T-Head/Alibaba specific extensions to the ISA
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<Jmabsd>
sorear: they have presold 2 billion CPU:s? lol
<sorear>
Jmabsd: no, they have sold 2 billion CPUs of their legacy "nds32" architecture
<Jmabsd>
so guys about the claim that SiFive's boot code is **not** open source: it's **not** true right?
<Jmabsd>
you have debunked it
<sorear>
Jmabsd: or more precisely that their partners have sold chips containing 2 billion nds32 cores
<Jmabsd>
what is the development budget to make a RISCV design at 5 or 4nm and place the order at TSMC or Samsung? :)
<Jmabsd>
jrtc27,jimwilson: so we have debunked it yea?
<sorear>
to the extent that it's relevant it's not true and to the extent that it's true it's not relevant
<sorear>
there are pieces of raminit code that aren't really documented (because sifive got them from another company), and the ZSBL is so small that the concept of "source" gets fuzzy
<Jmabsd>
great.
<Jmabsd>
i think last question by me today, in what timeframe will we have RISCV64:s as strong as Apple M1 or IBM Power9?
<sorear>
I suspect the aarch64 patents will expire before any direct equivalent appears
<sorear>
europractice doesn't have anything for tsmc below 28nm
<sorear>
note, tsmc is going to make you sign a *bunch* of NDAs about anything that could plausibly expose process or IP details to competing foundries
<sorear>
enjoy being called a traitor when you're in the position of not being able to talk about your chips :)
<sorear>
idk whether it'd cost you closer to $1M or $100M but I don't think there's a big market of people who want a low performance riscv chip, are willing to pay $1000+ per chip, and also don't care that you're going to be prevented from releasing most information about it and boot code
<sorear>
if you _do_ have a few million burning a hole in your pocket, can spin up a company, and only want chips for personal use, knock yourself out. i just don't think there's any way to get much traction in the 'freedom segment'
<sorear>
you could put BOOM on a chip but without process-specific physical design optimization the frequency will be several times worse than it could otherwise be. you could license a core from someone, but the optimization will be incomplete for the newer processes and the licensable cores are all fairly small / low-IPC cores
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<Jmabsd>
sorear: oh. when do the aarch64 patents expire?
<sorear>
conservatively, 2033
<sorear>
since the general public could buy aarch64 (iphone 5s) in sept 2013
<Jmabsd>
ah, regarding SiFive: "The SBE is the Self Boot Engine; i.e. the little embedded POWER CPU that starts the entire boot process off. On x86 etc. it's part of the ME/PSP, on the newer SiFive stuff it's part of the firmware that they don't want public."
<Jmabsd>
so apparently SiFive does not want their background management engine's sourcecode to be public? if so that's a total disaster, sorear jimwilson
<sorear>
if someone is calling a "CPU" "part of the firmware" they have no idea what words mean
<Jmabsd>
maybe some customer support whatever. but it is a CPU core
<sorear>
the hifive unleashed has a background management core, it's riscv based and you can run whatever you want on it
<sorear>
unmatched too
<sorear>
although if you keep quoting such an incoherent document as gospel truth I don't know how to argue against that
<sorear>
huh, the 5S came out a year before Arm's own aarch64 evaluation board
* pabs3
wonders why the SBE is POWER instead of also RISC-V
<xentrac>
Jmabsd: not having done it, I'm guessing you could ship a RISC-V chip in an old process node like 35nm for under half a million dollars in under three years
<xentrac>
sorear: haha "competing foundries"
<xentrac>
I think shipping a less obsolete chip is likely to take you 5 years and tens of millions of dollars
<sorear>
180nm seems to be the "old process node" of choice, I haven't seen much new 35nm but 180 refuses to die
<xentrac>
180nm is good for analog, I hear. smaller feature sizes have too much noise
<xentrac>
my experience on this count is limited to blowing up people's speakers with my Arduino though
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<xentrac>
so that's just my understanding of what Camenzind's book says
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<Jmabsd>
sorear,xentrac,jimwilson: Actually on the default Linux deployment on the current SiFive Unmatched, what is actually running on that fifth service core??
<drmpeg>
Nothing. It's disabled.
<Jmabsd>
sorear: is your idea that AARCH64 might actually win over RISCV64 in the long term just because AARCH64 will become free around year 2033?
<Jmabsd>
drmpeg: ah ic. okay great that it's disabled, so it's just there fore demo/showcase purpose?
<Jmabsd>
like "we have this tiny low wattage core here that you Could do service stuff with.
<Jmabsd>
If we would have done it, it'd have been closed source. But now we just skip it altogether"?
<drmpeg>
It could be open source. It's just another core. But it can't be another Linux core.
<Jmabsd>
yeap ic.
<Jmabsd>
drpmeg: it is integrated with the system so it doesn't have access to RAM fully or why can't it be a linux core - anyhow i guess this is "standard"
<drmpeg>
It doesn't have all the architecture features to run Linux.
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<drmpeg>
It's only rv64imac
<Jmabsd>
Great, thanks for clarifying
<drmpeg>
I guess technically, it could run Linux. But no MMU and soft floating point.
<Jmabsd>
No MMU -> oh dear. Better keep it off.
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