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<mcrod>
hi
<zid>
heat I wrote A MACRO today :(
<mcrod>
i wrote nothing today because writing code on a mac is just unbearable
<zid>
mac has vim and gcc though
<mcrod>
or any laptop really
<mcrod>
no no, I just hate laptops
<mcrod>
my PC is out of commission for another few weeks
<zid>
buy it a keyboard
<zid>
and a monitor
<zid>
and you have a PC again
<mcrod>
yes
<mcrod>
I need a USB-C adapter for my mouse though
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<heat>
zid, are you a GNU PROGRAMMER now
<zid>
define _(x) {sizeof(x)-1, x}
<zid>
do u like it
<zid>
it pascalifies strings
<zid>
so I could remove a strlen from my code
<heat>
BASED
<zid>
heat I need faster rams
<zid>
mine is too slow for AoC
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<heat>
faster rams or more cache?
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<zid>
just remembered I forgot to re-enable turbo
<zid>
I bet AoC is way faster at 4.8GHz rather than 3.8GHz
<zid>
179us!
<heat>
lol why did you disable it
<zid>
was debugging a crash, but I think it was a hyper-v bug
<zid>
was getting machine checks
<zid>
so I tried lowering my clocks and increasing my volts and stuff
<heat>
oh damn that's some straight up single core MEGA TURBO SPEED you left on the table
<zid>
then left it that way afterwards because I was only reading light novels in summer
<zid>
first day of winter is a good day to turn them back up
<zid>
WINTER MODE ENGAGE
<heat>
gotta go warm
<heat>
the new intel cpus double as a heater
<zid>
My 5800x is a real pain in the arse to overclock compared to my sandy :(
<zid>
it has a million tunables and I don't understand what any of them are because they've been like, abstracted over
<zid>
what's "Precision Boost Overdrive All Cxx Core Offset Multiplier 7" or whatever
<heat>
maybe they uhhh dont really matter
<zid>
rather than just setting my voltage offset and max core multiplier
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<heat>
i wouldn't be surprised if overclocking hasn't been all that effective for MEGA HYPER TURBO BOOST cpus
<zid>
I don't want PRECISION BOOST OVERDRIVE, I want a voltage setpoint for idle, a voltage setpoint for full turbo, and a max multi
<zid>
yea it does almost nothing
<zid>
They just turbo until power limit or 90C then stop
<heat>
sounds aight?
<mcrod>
I would like to get a new CPU, because I think this one is actually busted somehow
<zid>
I want my 1650 back
<mcrod>
but I'm not spending $800 on a 9800X3D
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<zid>
at least it has like an 'auto' setup tool
<zid>
that just keeps raising the clocks and voltages until it gets too hot and crashes
<heat>
ok mcrod send me this cpu
<heat>
with no cum on it, preferentially
<heat>
i know you're sick and twisted and might do that
<mcrod>
yes, i cum thermal paste
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<heat>
hot.
<heat>
actually
<heat>
cold.
<zid>
and this is a good excuse for me to add a bunch of cardboard shims to all my fans to get them to shut up
<zid>
now that they're spinning and being annoying
<zid>
£8 fan + cardboard >>>> £25 noctua
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<rrq>
about switching to aarch32 for a cortex-a53; is that done separately for each thread? if so, does each thread have their own system registers, or are some system registers shared? I'm looking for documentation about it
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<Ermine>
isn't overclocking about pouring liquid nitrogen onto your tech until it shows some mind blowing clock rates?
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<clever>
rrq: aarch32 mode, is just using the lower 32bits of most of the 64bit registers
<clever>
typically, the kernel runs in aarch64, and uses eret to return to a 32bit userland
<clever>
within the saved registers, is the previous mode (user vs kernel) and the bit width
<rrq>
each core thread switched separately?
<clever>
so when creating a thread/process, you just make up a fake "previous mode" that has the right values, and "return" to it
<clever>
yeah, each core can be in any mode
<rrq>
is there doc on which system registers are shared vs per-thread?
<clever>
i believe nearly everything is per-core
<clever>
except one of the timer values? and peripheral stuff
<clever>
per-thread, is up to your kernel, what it swaps out when changing threads
<rrq>
ok. this is boot sequence before kernel.. I want to boot "linux armhf" (i.e. aarch32)
<clever>
i think you can use eret to drop from 64bit kernel to 32bit kernel
<rrq>
so I suppose all threads need to switch and then only one is used to boot the kernel
<rrq>
while the other sits in some spinlock(?)
<clever>
yeah, all threads will need to be in 32bit mode when entering the kernel
<clever>
on platforms like the rpi, 3 of the cores sit in a WFE loop waiting for a PC to start at in a spin-table
<clever>
on better platforms, they use PSCI to start the cores up via firmware in EL3
<clever>
with PSCI, EL3 would always be in aarch64 mode, and when directed, it will eret down to EL2/EL1 in the desired bit width
<clever>
and when directed, the cpu can be forced back to EL3 to re-park a core
<clever>
and each core can do that seperately
<rrq>
thanks. yes I have a pi3 box .. with cortex-a53 ..
<clever>
for the rpi specifically, there is non-standard jank
<clever>
a special control register that makes the cpu start in aarch32 mode, from the very first opcode
<clever>
arm_64bit=1 and arm_64bit=0 in config.txt control that
<clever>
then its just in 32bit mode from the start, and you can ignore all the armv8 stuff
<rrq>
ah.. I'll see if I can find that; would be perfect for my use case :)
<rrq>
"config.txt" ? ... that's still after some u-boot steps?
<klys>
u-boot reads config.txt iirc
<klys>
it's part of the mkimage output
<clever>
klys: ive never seen that before
<clever>
config.txt happens before u-boot, in the firmware on the VPU
<klys>
it seems you have some stuff that can get at the vpu on pi3 or earlier iirc
<clever>
for the pi0-pi3 models, bootcode.bin is unsigned, so you can just replace all the VPU blobs
<klys>
other arches use u-boot, mebby not pi
<rrq>
config.txt is mentioned in trusted-firmware-a source
<clever>
rrq: link?
<clever>
when using the official firmware, with stock raspi-os, there are ~5 stages to the boot
<rrq>
docs/plat/rpi3.rst
<rrq>
right; I have an "orangepi 3 LTS" though
<clever>
ah, thats a totally different beast, and i dont know its internals
<klys>
I have a pi4b 2gb and riscv nezha board and sipeed k210 riscv
<clever>
the config.txt things in rpi3.rst, are to get the firmware to co-operate with ATF
<clever>
for the pi0-pi3 family, the 5 stages are:
<clever>
stage 0, the boot rom, it typically loads bootcode.bin from a fat fs on an SD card
<clever>
but the pi3 also supports loading it from fat on usb, or tftp
<rrq>
ok; platform is an allwinner/sun50i_h6
<clever>
stage 1, bootcode.bin, it gets loaded to 0x8000_0000 and then it jumps to 0x8000_0200, and this blob brings the dram controller online before loading start.elf from the same place
<clever>
stage 2, start.elf, contains all of the runtime services, and the rest of the bootloader
<bslsk05>
github.com: tools/armstubs at master · raspberrypi/tools · GitHub
<clever>
stage 2 includes pre-built copies of the armstub for each model
<clever>
a copy of the armstub for the right model, gets dropped at arm physical 0 (the reset vector)
<clever>
the linux kernel (stage 4), dtb, and initrd, get dumped somewhere in ram (varies, and can be configured)
<clever>
and the armstub is patched, to know where the kernel/dtb are
<klys>
clever have you hacked 4b yet just curious
<clever>
and the dtb is patched to know where the initrd is
<rrq>
clever: thanks I'll see if I can use that
<clever>
then the arm is set loose on the stub, and things boot from there
<clever>
klys: for the pi4, the difference is that stage1 typically lives on SPI flash, but a recovery.bin on SD has priority, for "unbricking", in both cases, it must be signed with an hmac-sha1 key
<clever>
however, they made the mistake of stage2 (start4.elf) being unsigned, and the boot rom still being on the bus
<clever>
so a custom start4.elf can dump the rom, then a bit of decompiling later, and i have the hmac-sha1 keys
<clever>
so i can now sign custom stage1/recovery.bin files
<klys>
so eh, stage1 is that bootcode.bin ?
<clever>
yeah
<clever>
on pi0-pi3, stage1 is called bootcode.bin, and primarily lives in /boot on the boot disk
<klys>
and you have it for the apu in a disassembly?
<clever>
on pi4, stage1 primarily lives in the SPI flash
<clever>
but a recovery.bin on SD is also a valid stage1, and has priority, for when SPI is bricked
<clever>
apu?
<klys>
it runs on the apu at boot?
<klys>
ergo the arch must match
<clever>
the VPU, yeah
<klys>
ok
<clever>
stage1 must be valid VPU assembly
<klys>
is it annotated assembly that you have uploaded or is it just somewhere on the back burner
<clever>
for both of them, its a 500mhz differential clock, and then 2-4 lanes of differential DDR data
<klys>
is the dsi port tested with respect to the above or were you just using hdmi?
<clever>
thats just what the specs say, i dont have any hardware capable of testing it
<clever>
for the pi0-pi3 family, the 2d core start with the HVS (something video scaler?)
<clever>
it has 3 channels, and a chunk of display-list memory
<clever>
for each channel, you configure a resolution, if its interlaced, and where it starts in the display-list memory
<clever>
at that starting location, you list off every sprite to display on the screen
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<clever>
for an unscaled plain rgb image, it takes up 7 x 32bits of display-list memory, per sprite
<clever>
plus a single 32bit value to terminate the list
<clever>
every time the output FIFO on the HVS has room for 1 scanline of image data, it will parse the display-list, find all sprites covering the next scanline, fetch image data from dram, scale&composite it into the FIFO, and advance the state by 1 scanline
<clever>
and with 3 channels, its time-sharing that computation over 3 display lists, keeping 3 FIFO's fed
<klys>
recently I was breadboarding access to a 71256SA25TPG sram chip using dip switches, an astable 555 timer set for ~1sec, and leds
<clever>
channel 0 can drive either DSI0 or DPI
<clever>
channel 1 can drive HDMI or VEC(composite video)
<clever>
channel 2 can drive DSI1 or SMI
<clever>
you can never drive 2 things with a single channel
<clever>
on the HVS side of the fifo, its very bursty and laggy, since it has to deal with dram latency and bus contention
<clever>
the pixel valve (PV) side however, is running in lock-step with the pixel clock, reading the HVS FIFO, 1 value per pixel
<clever>
the PV defines all of the video timing parameters, generates hsync/vsync, the blanking signals, and turns the flow of pixels on/off (hence pixel valve)
<klys>
VEC composite is new on me, I have dealt with S-video and composite, just never with an HDMI connector.
<clever>
internally, the VEC can operate in 1, 2 or 3 channel mode
<clever>
3 channel mode gives you RGB and YPbPr
<clever>
2 channel mode gives you s-video
<clever>
and 1 channel mode is composite
<clever>
but channels 2/3 arent wired up on any rpi board
<klys>
so 3 channels is component video
<clever>
and RPI has never provided example code on how to actually use the channels
<clever>
so we are stuck in 1 channel mode
<klys>
with the appropriate connector, I gather
<clever>
for the pi1, the video was just on a dumb old RCA jack
<clever>
for the pi2/pi3/pi4, its a TRRS headphone jack, left+right+video on the same connector
<clever>
for the zeros and pi5, its a 1 pin 0.1" header that isnt populated
<bslsk05>
iosoft.blog: Raspberry Pi Secondary Memory Interface (SMI) – Lean2
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<clever>
basically, the hardware will presnt a 6 bit address on 6 pins
<clever>
then wiggle the r/w, and output-enable pins in a certain pattern (depending on the mode)
<clever>
and then either read or write 18 bits of data, on another 18 pins
<clever>
so, you could whack some SRAM onto the rpi, with 64 rows, of 18 bits each
<clever>
and then use SMI to access it at high speed
<clever>
or, you could take the good old HD44780 LCD driver
<clever>
rig addr bit 0 to command/data, addr bit 1 to chip-select, and then blast it with a full frame under hw control
<clever>
then slap a raw NAND chip on the same pins, use addr bit 2 as the NAND chip-select, and now you can talk to both at once
<clever>
addr 0 and 1 are lcd, addr 4 is nand
<klys>
I'll be off it's time to rest for now
<clever>
same, its 5am!
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<rrq>
anyone still around? is there also separate MMU for the threads, or is that to be set up by 1 thread ?
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<GeDaMo>
The MMU is a hardware unit, there's one per core
<GeDaMo>
Normally, processes each have their own address space, threads share an address space within a process
<GeDaMo>
Actually, I say one MMU per core but I'm not sure :|
<ring0_starr>
wouldn't it need to be one mmu per core
<GeDaMo>
Does the address translation happen before or after the caches?
<ring0_starr>
at the same time as the virtual index calculation, no?
<Affliction>
I figure there'd be at least some per-thread resources. At very least the register that backs CR3, for instance. Precise details very likely differ with microarch
<GeDaMo>
I mean, what's stored in the caches, virtual addresses or real addresses?
<ring0_starr>
ive been looking for the answer to that question myself today, but all i get are college computer architecture course powerpoint slides, which have some lines and diagrams and nothing really of substance on their own
<ring0_starr>
from what i can understand, most modern cpus use VIPT which hashes the vpn and then somehow uses the physical address as the "tag" ?? nothing i read goes into specifics of how
<Affliction>
I don't have a real answer, but given that I have used aliased virtual pages without everything going wrong, the CPU seems to at least provide the illusion that it's physical memory that's cached
<ring0_starr>
piecing together information from like 5 different websites the tag is the top N bits of the physical address, N being decided by the internals of the cache
<ring0_starr>
not like we really can do anything with this information at the software level
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<geist>
it's a single mmu per logical hardware thread yes
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<heat>
hey i just met you
<heat>
and this is craaaaaaaazy
<heat>
but here's my number
<heat>
so call me maybe
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<mcrod>
no
<nikolar>
heat, you ok
<heat>
yes why would i not be okay
<heat>
i'm quite negatively surprised there are no carly rae jepsen fans here
<nikolar>
Lol are you a fan of hers
<nikolar>
Name 3 of her (orher) songs
<heat>
i only like her 2011 songs
<heat>
after 2011 i think she got paul mccartney'd and replaced with a worse clone of her
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<nikolar>
Lol
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<heat>
do you think the discord people know who carly rae jepsen is
<mcrod>
yes
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<nikolar>
Maybe they are too young
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<kof673>
i know that song but don't know if you can do much with it. no time for love dr. jones > Hercules Fights a Bear 1983 you will note cassiopeia is redhead with blue eyes...other characters at this alchemy location include disney's the little mermaid lol green forest here lol