04:16 <MoeIcenowy> _florent_: maybe the reset signal should be synced to oscillator clk domain?

06:15 <_florent_> MoeIcenowy: Sorry, I haven't looked at it closely for now, but this is something working on other PLL wrappers (at least Xilinx, Lattice).

19:24 <josuah> someone I am working with got the Verilog export working! With a few manual edits on the exported varilog though, which I am currently integrating into LiteX so that the out-of-the-box .v works

20:30 <_florent_> josuah: In fact, the different generator in LiteX (litex_periph_gen/litex_soc_gen) and in the cores (litedram_gen, litepcie_gen, etc...) also have these purpose. As soon as you integrate non trivial cores, you need to specialize the logic/primitives, so it's generally better to generate for a specific vendor/flow.

20:51 <josuah> _florent_: this might have been a better way to go, if only I was not so stubborn ^_^'

20:51 <josuah> thank you for pinging me back about it

20:53 <josuah> we might have been lucky in the cores we had to play with

20:54 <josuah> anything using a SERDES might be striked out of the generic export

22:57 <josuah> this is also the decision of the client, and while I am glad to show the various experiments we do in the form of [RFC] pull-requests...

22:58 <josuah> ... I hope this does not interfer with the ongoing work, there is much to do, such as the Amaranth compat layer back-end