_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<davebee> I'm trying to add a LiteDRAMDMAReader to a DRAM on a vexriscv CPU. The DRAM is currently on the wishbone bus and has an 8k l2 cache. Not sure how to go about adding it and not sure what problem might be caused by the cache. Are there ways of invalidating the cache after a DMA write?
<davebee> Can I just do sdram.crossbar.get_port() to get a port on the dram? Is this all I need to pass to the LiteDRAMDMAReader?
<davebee> Looking good so far. Just need to wire the source up. Sorry I've been talking out loud.
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