_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<tpw_rules> _florent_: hi, i sent several PRs recently to litex and wondered if there was any feedback? it was mostly about quartus stuff which seems a bit under-loved, is there someone around suitable to review them?
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<_florent_> Thanks tpw_rules for the PRs! Sorry and sorry for the delay. I should have merged at least one of the PR I think. For the Quartus one, it should be fine and I'll try to review this soon.
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<_florent_> For https://github.com/enjoy-digital/litex/pull/1433, as a side effect, the BIOS was no longer smooth (we were only getting characters per bursts), so I need to have a closer look.
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<_florent_> For https://github.com/enjoy-digital/litex/pull/1448/files, this should be fine, just want to have a closer look.
<_florent_> jevinskie[m]: interesting, thanks for sharing
<tnt> might also want to check effect of the jtag patch on litescope
<_florent_> tnt: indeed, I also thought about this/you when seeing the PR. If you have the time to do a test and provide feedback, I'm interested :)
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<tpw_rules> _florent_: strange about the JTAG uart, i did not notice any bursting like that. the BIOS terminal still worked great for me. feedback is welcome, i only have the one board and two adapters
<tpw_rules> what OS and JTAG adapter did you use? imo those would be more likely to cause the issue
<tnt> FTDI based ones (Digilent HS)
<tnt> That's also what the Arty mentionned in the issue has built in.
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