_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<jevinskie[m]> Ah, just AsyncResetSynchronizer right? I think I was reading the docs wrong and missed the async setting part
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<tnt> jevinskie[m]: if your logic is clocked off SCK, AsyncResetSynchronizer really help.
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<alainlou> hey everyone I'm having some trouble getting the code to fit in block RAM on my Cyclone IV board "RZ-EasyFPGA"
<alainlou> there were two options I was considering:
<alainlou> 1. any way to reduce code size?
<alainlou> 2. there's a SPI flash chip which I can use as ROM but it's also the one used for programming "Altera EPCS" - would it be bad if I connected pins from the FPGA to "AS programming" header to try to use this flash chip?
<alainlou> any help is appreciated!
<tnt> jevinskie[m]: I just realized I messed up my sentence when rephrasing it ... it's missing "won't" ... it "won't really help".
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<david-sawatzke[m> alainlou: I don't know this board, but I assume the spi flash is connected directly to the fpga to load the bitstream.
<david-sawatzke[m> If the flash has enough space to fit both the bitstream (if needed) and the programm, you can use the litex spi core to mmap the flash contents.
<david-sawatzke[m> Then you can tell the bios to jump to the adress where your firmware starts in the flash memory in the wishbone address space.
<david-sawatzke[m> This is done by setting ROM_BOOT_ADDRESS to the right address, like done here for rom boot https://github.com/enjoy-digital/litex/wiki/Load-Application-Code-To-CPU
<alainlou> <3 thanks david!
<alainlou> just to clarify, this is for the BIOS code, not even application code - would the same solution apply?
<david-sawatzke[m> Oh, you're talking about the bios. There is a mechanism to boot directly from an address without having the bios in the bitstream
<david-sawatzke[m> But you can also reduce bios code size with things like:
<david-sawatzke[m> self.add_constant("SDRAM_TEST_DISABLE")
<david-sawatzke[m> and `builder = Builder(soc, **builder_options, bios_options=["TERM_MINI"])`
<david-sawatzke[m> But I'd recommend searching the bios code for more things like this
<alainlou> awesome!
<alainlou> > There is a mechanism to boot directly from an address without having the bios in the bitstream
<alainlou> not quite sure what you mean by this?
<alainlou> is it like the link you gave for application code but for BIOS code as well?
<david-sawatzke[m> The link I gave is for application code
<alainlou> yup, but ur saying there's something similar for bios code as well?
<david-sawatzke[m> I'm don't remember how the other one works
<alainlou> ah no worries, I'll have a look around
<alainlou> thanks for all the help!
<david-sawatzke[m> Yeah, it's primarily intended for if you just want to use application code without any bios, but might (shoud) also work for storing the bios externally
<jevinskie[m]> tnt: is that because it uses two FFs and introduces a cycle delay? I made a single stage one with one FF that seems to work for my needs. I think metastability won’t be an issue since the CS# setup and hold times should be long enough
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