<alainlou>
maybe a noob question, but need some help again on trying to get the litex BIOS to work on my (currently unsupported) Cyclone IV board . . .
<alainlou>
Right now my board (platform and target) files do not use any flash or off-chip DRAM
<alainlou>
With @tcal's help I've been able to build an FPGA bitstream and flash my board! thanks tim! I do get the nice LED "snake" animation, which is something, however, the output from the serial port is really wonky.
<alainlou>
I've tried combinations of these CPUs and RISC-V compiler versions:
<alainlou>
- vexriscv minimal, serv
<alainlou>
- riscv compiler from SiFive centos6 and ubuntu14
<alainlou>
all of them produce this output
<alainlou>
```
<alainlou>
[azl@fedora ~]$ lxterm /dev/ttyUSB0
<alainlou>
�yrRgI�������
<alainlou>
���
<alainlou>
�
<alainlou>
������
<alainlou>
��
<alainlou>
�.�Vi�^.�V�������
<alainlou>
�
<alainlou>
��{
<alainlou>
��
<leons>
Have you tried attaching a scope to the device? I‘m unfamiliar with Intel FPGAs but maybe they feature a logic analyser similar to Xilinx‘ ILA core
<sorear>
How confident are you in the correctness of the serial port configuration on both sides?
<leons>
Yeah, I‘d highly suspect a baudrate related issue
<leons>
That could of course also be caused by wrong clocking internally. A good sanity check is whether the LED racer has a period of exactly one second. That gives a rough indication of whether `sys_clk` has the expected frequency
<alainlou>
hmm looked at it for 10 periods, was around 10 seconds on my stopwatch - seems like I need to maybe learn SignalTap for real this time :D
<alainlou>
@sorear, for configuration it'd be just setting the right pins and clock frequency on the board and then the correct baud rate and uart settings on my computer right?
<alainlou>
sanity check: 115200 8N1 is the up-to-date setting right?
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<ChuckM>
Ok, n00b question. I want to import the icebreaker but 'from litex_boards.platform.1bitsquared_icebreaker import Platform` errors out on the 1bitsquared?
<ChuckM>
okay got past that by importing icebreaker instead, and moving past litex.cores.ram becomes litex.soc.cores.ram, now missing the definition of SubSignal