01:03 <jevinskie[m]> Yeah crossover uart and litex server connected by jtagbone :)

01:17 <tpw_rules> how do i set that up? my whole problem is it doesn't compile when the uart is set to crossove

06:21 <_florent_> tpw_rules: your issue could be be related to the false paths constraints that are not applied correctly

06:21 <_florent_> https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/sqrl_acorn.py#L107

06:22 <_florent_> I wanted to improve this and avoid the fixed names, but haven't been able to look at it yet

06:23 <_florent_> can you share your generated files to see if I'm able to built on my machine (still with Vivado 2018.2)?

12:09 <DerekKozel[m]> vomoniyi: Do you see the board with the litepcie_util info command or in the dmesg log when the kernel module loads? Or is it always the Unsupported device 255 error?

12:13 <DerekKozel[m]> A way of checking if the FPGA board is seen at all is to run `lspci` and check for an entry for:

12:13 <DerekKozel[m]> Memory controller: Xilinx Corporation Device

12:17 <vomoniyi[m]> When I run lspci, I see the board

12:22 <DerekKozel[m]> _florent_: I was just looking back at the reference bitstream you sent and realized that you said you load the FPGA, then reboot the computer. Doesn't that clear the bitstream?

12:22 <DerekKozel[m]> https://libera.irclog.whitequark.org/litex/2021-07-29#30359549;

12:22 <tpb> Title: #litex on 2021-07-29 — irc logs at whitequark.org (at libera.irclog.whitequark.org)

12:37 <tnt> DerekKozel[m]: Why would it clear the bitstream ? Board should stay powered.

12:38 <DerekKozel[m]> Hey tnt. Ah, I was guessing that the board would be power cycled when the computer was. But a reboot I guess preserves the power rails

12:38 <tnt> Well, he said _reboot_, not power cycle.

12:39 <tnt> If you power it off and on ... yeah, it'll clear it.

12:39 <DerekKozel[m]> Ok, that's good to know. I'm slightly surprised that a reboot doesn't toggle the power rails to peripherals, but that's useful.

12:42 <DerekKozel[m]> vomoniyi, I just loaded florent's example image and rebooted. The kernel is now picking up the FPGA after the init.sh script. Try the litepcie_util info command and if that works try the dma test

12:46 <vomoniyi[m]> Derek Kozel: Both commands worked

12:48 <DerekKozel[m]> Ok! Can you try loading a freshly built FPGA image from the latest LiteX, then reboot (run the `reboot` command), and try the init.sh and util tests again? Hopefully it's the reboot step that was missing before.

13:05 <vomoniyi[m]> Yep, it's all working fine again.

14:35 <tpw_rules> _florent_: i guess, but i didn't try any special options

15:56 <mongo505> I just came across litex in search of a linux utility for programming bitstreams onto FPGAs. Does litex include such a utility?

15:58 <leons> openFPGALoader does the job for me

15:58 <leons> Alternatively openocd scripts are very flexible

15:58 <leons> And seem to have a somewhat broad FPGA support, at least in the Xilinx universe

16:02 <mongo505> cool, does it support writing to connect SPI flash?

16:03 <mongo505> *connected

16:03 <leons> As for your question, I think LiteX simply uses these utilise and does not ship its own

16:03 <mongo505> looks like it does, thanks for the info

16:04 <leons> openFPGALoader does support writing to the SPI flash at least on the Arty A7 Board, I can confirm that :)

16:17 <mongo505> hmmm...according to this it does: https://github.com/trabucayre/openFPGALoader/blob/master/doc/board-compatibility-list.md

16:18 <mongo505> I've had a lot of success with xc3sprog, but need the ability to command it to boot from SPI flash after programming

16:26 <Wolf0> https://twitter.com/Wolf9466/status/1430562454162100230 - bets on how fast Versal's HBM will really be? :"3

16:26 <Wolf0> *:3

20:20 <jevinskie[m]> A+ change with registering the litescope signals. Cuts my build time of the arty litedram demo in half!