dgilmore changed the topic of #fedora-riscv to: Fedora on RISC-V https://fedoraproject.org/wiki/Architectures/RISC-V || Logs: https://libera.irclog.whitequark.org/fedora-riscv || Alt Arch discussions are welcome in #fedora-alt-arches
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<dtometzki> hey cool
<dtometzki> davidlt: then we can hope in the next linux release is jh7110 mainline
<davidlt[m]> I wouldn't expect anything until 6.4 at least.
<davidlt[m]> 6.4 might be able to boot, UART, maybe network and SD card support.
<davidlt[m]> The goal of the 1st patchesets is to just boot mainline, the rest isn't really important.
<davidlt[m]> They started upstreaming something like 2 months before HW showed up IIRC.
<davidlt[m]> It's not like Intel/AMD/IBM where things go upstream 1-2 years before hardware show up.
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<cwt[m]> <davidlt[m]> "It's not like Intel/AMD/IBM..." <- *before* yep 🙃
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<somlo> ok, so CONFIG_SOC_STARFIVE=y is *not* a problem on LiteX/Rocket. Now trying ERRATA_THEAD=y...
<davidlt[m]> Oh, I thought those were tested already :)
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<somlo> I tried turning of "half" of the options on my list, then the other "half", and there's probably some member of each set that does something weird
<somlo> now I'm turning them on one by one, and then turning back off the ones that cause me trouble :)
<somlo> so, the earlier test was inconclusive :)
<somlo> It's been literally decades since I actually had to think things through carefully beforehand, rather than just doing a tight trial-error loop when debugging something :)