<d1b2>
<Olivier Galibert> @josuah_dem an extra domain on what?
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<d1b2>
<josuah_dem> I thought inserting a new clock domain on the module you wanted reduced, but it looks like you want to reduce an existing module's sync frequency?
<d1b2>
<josuah_dem> For instance, anything that needs a particular slower clock domain could get a slow clock domain that takes a parameter to arbitrarily reduce the clock speed. The "slow" clock domain becomes the new sync and is used everywhere instead of sync in that module? I am also curious about how to best play with different clock domains.
<d1b2>
<Olivier Galibert> Just to clarify, my use case is the wd1772 in the context of the atari st emulation. The system clock is ~32MHz. The wd itself has a 8Mhz clock as input, which I plan to have as the 32+1/4 enable. Then internally the wd divides it by 2 if in fm, doesn't divide in mfm, to generate a first clock used by the pll and the communication with the drive in general. The pll generates from that two 0.5/0.25MHz clocks with offset
<d1b2>
phases. My aim would be to have those three clocks as domains, to make the code more readable. And I wouldn't have CDC issues since they're all 32MHz + some enable
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<d1b2>
<josuah_dem> Would it not work with a regular m.d.new_clock_domain += become_skynet.eq(user != Elon_Musk)?
<josuah>
what I do is I clone all Amaranth projects I come acros in a same directory, and whenever I want some answer for an undocumented thing, I grep -R that directory
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<d1b2>
<Olivier Galibert> joshua what you're missing is the difficulty of combining multiple enables together, especially since you don't have access to one of them (there is not EnableSignal(domain) iirc)
<d1b2>
<Olivier Galibert> I don't want to be rude, but try re-reading the question, because I think you missed the important points
<d1b2>
<Olivier Galibert> as far as I understand a domain is a quadruplet (name, base clock signal, enable signal, reset signal), but I'm not sure enable is reachable (yet), and combining enables is nontrivial (could be a simple and though now that I think about it)
<d1b2>
<Olivier Galibert> partially. Two problems with that compared to what I would want. First, creating a new clock signal is probably a bad idea for fpga implementation, having one clock and enable signals is better
<d1b2>
<Olivier Galibert> second, I'd like the wd1772 not having to know about the composition of its incoming sync
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<DeVector[m]>
other than Clock gating, I'm not sure how to go about it, only way I can think of is, deriving two clocks from ClockSignal("sync") and then, making them as new ClockDomains
<DeVector[m]>
in xilinx fpga, I think you can use those IO buffers with enable to get your target clock
<d1b2>
<Olivier Galibert> well, in the cyclone v every ff has an enable input, don't xilinx ffs have one?
<d1b2>
<devansh1729> Yes, there is, in vivado there is one attribute to enable clock gating through ff to eliminate the clock skew, but idk how to do that in amaranth
<d1b2>
<Olivier Galibert> amaranth->yosys synthesizes dffe when you have a domain + m.If(enable) or a domain with an EnableInserter on top of it
<d1b2>
<Olivier Galibert> just checked the artix-7 logic block, all ffs have a "CE", clock enable, input
<d1b2>
<Olivier Galibert> suspect it's the same for the other 3 series
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<whitequark>
virtually every FPGA has DFFEs
<whitequark>
however CE is synchronous to the clock
<whitequark>
so you could emulate CE with a 2-LUT connected to D, Q, and whatever circuit you had connected to D before, and it'll work the same